Ministry of Education
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Dr Anuj Grover

vidwan id: 105051
Male

Associate Professor, Department of Electronics and Communication Engineering
Indraprastha Institute of Information Technology Delhi (IIIT Delhi)

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Expertise

  • Computer Science Hardware and Architecture

Publications

Total Articles 55
Books 0
Proceedings 0

Publications

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Scopus

Citations 381
h-index 9

CrossRef

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Citations 269
h-index 7
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Professional Recognition

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Community & Membership

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IEEE - Circuits and System Society - Delhi Chapter

2021
Secretary

IEEE

2020
Senior Member

Bio

Ultra Low Power In-Memory Compute for edge computing and machine learning applications, Safety and security in hardware,Error resilient energy efficient systems.

Personal Details

  • Male
  • Associate Professor , Indraprastha Institute of Information Technology Delhi (IIIT Delhi)
  • Indraprastha Institute of Information Technology Delhi, Okhla Industrial Estate, Phase III, New Delhi
Ph.D
Other Institute 2015
Associate Professor Jan 2020 – Present
Indraprastha Institute of Information Technology Delhi (IIIT Delhi) | Department of Electronics and Communication Engineering
Assistant Professor Feb 2019 – Dec 2019
Indraprastha Institute of Information Technology Delhi (IIIT Delhi) | Department of Electronics and Communication Engineering
Teaching Assistant Jun 2003 – Dec 2003
University of California, San Diego, U.S.A.
Research Associate Sep 2002 – May 2003
University of California, San Diego, U.S.A.

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Scholarly Work

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Design for Test in Advanced Automotive SoCs

University Gautam Buddh University
Year 2019
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Scholarly Publications

A 0.47V-1.17V 32KB Timing Speculative SRAM in 28nm HKMG CMOS

Open Access
Conference Paper
Year: 2020.
Authors: Kumar M.;Grover A.;Dikshit V.;Gupta V.
DOI 10.1109/VDAT50263.2020.9190622
1 1

Comparative Analysis and Implementation of Single-ended Sense Amplifier Schemes using 65nm LSTP CMOS Technology

Open Access
Conference Paper
Year: 2020.
Authors: Verma V.;Akhtar F.;Grover A.
DOI 10.1109/VDAT50263.2020.9190401
1 1

A 81nW Error Amplifier Design for Ultra Low Leakage Retention Mode Operation of 4Mb SRAM Array in 40nm LSTP Technology

Open Access
Conference Paper
Year: 2018. Volume: 2018-September , Pages: 19-22 .
Authors: Mamgain A.;Grover A.
DOI 10.1109/SOCC.2018.8618569
1 2

Comparison of SRAM cell layout topologies to estimate improvement in SER robustness in 28FDSOI and 40 nm technologies

Open Access
Conference Paper
Year: 2017. Volume: 711 , Pages: 414-420 .
Authors: Ilakal A.;Grover A.
DOI 10.1007/978-981-10-7470-7_41
1 1

New stable loadless 6T dual-port SRAM cell design

Open Access
Conference Paper
Year: 2017.
Authors: Ganguly A.;Goyal S.;Bhatia S.;Grover A.
DOI 10.1109/ISVDAT.2016.8064859
1

An effective test methodology enabling detection of weak bits in SRAMs: Case study in 28nm FDSOI

Open Access
Conference Paper
Year: 2017.
Authors: Batra N.;Gundu A.K.;Hashmi M.S.;Visweswaran G.S.;Grover A.
DOI 10.1109/ISVDAT.2016.8064868
1 2

A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM with 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS

Open Access
Article
Year: 2017. Volume: 64 , Issue: 9 , Pages: 2438-2447 .
Authors: Grover A.;Visweswaran G.S.;Parthasarathy C.R.;Daud M.;Turgis D.;Giraud B.;Noel J.P.;Miro-Panades I.;Moritz G.;Beigne E.;Flatresse P.;Kumar P.;Azmi S.
DOI 10.1109/TCSI.2017.2705116
13 18

LoCCo-Based Scan Chain Stitching for Low-Power DFT

Open Access
Article
Year: 2017. Volume: 25 , Issue: 11 , Pages: 3227-3236 .
Authors: Pathak S.;Grover A.;Pohit M.;Bansal N.
DOI 10.1109/TVLSI.2017.2735864
9 18