Ministry of Education
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Dr G S Visweswaran

vidwan id: 105057
Male

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Expertise

  • Telecommunications

Publications

Total Articles 48
Books 0
Proceedings 0

Publications

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Scopus

Citations 287
h-index 9

CrossRef

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Citations 204
h-index 7
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Bio

CAD of VLSI, Design of Digital, Analog and Mixed Signal VLSI Circuits

Personal Details

  • Male
  • Indraprastha Institute of Information Technology Delhi, Okhla Industrial Estate, Phase III, New Delhi
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Visiting Faculty Jul 2018 – Jun 2022
Indraprastha Institute of Information Technology Delhi (IIIT Delhi) | Department of Electronics and Communication Engineering

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Organisation (0)

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Co-Authors (11)

Anshul

Prof Anshul Kumar

Indian Institute of Technology Delhi

Anuj

Dr Anuj Grover

Indraprastha Institute of Information Technology Delhi (IIIT Delhi)

B.

Prof B. Bhaumik

Indian Institute of Technology Delhi

G.S.

Prof G.S. Visweswaran

N/A

Maneesha

Dr Maneesha Gupta

Netaji Subhas University of Technology

M.

Prof M. Balakrishnan

N/A

Mohammad

Dr Mohammad S. Hashmi

N/A

Preeti Ranjan

Prof Preeti Ranjan Panda

Indian Institute of Technology Delhi

Pragya

Dr Pragya Varshney

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Prof Shiv Dutt Joshi

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Prof Shouribrata Chatterjee

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Scholarly Work

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Scholarly Publications

Design and Analysis of Voltage Control Function Generator Using Highly Linear CCII

Open Access
Conference Paper
Year: 2020.
Authors: Shweta Kumari ., G. S. Visweswaran ., Lily Kumari .,
DOI 10.1109/INDICON49873.2020.9342469
2 1

A 0.8V V<inf>MIN</inf>ultra-low leakage high density 6T SRAM in 40nm CMOS technology using repeated-pulse wordline suppression scheme

Open Access
Conference Paper
Year: 2019. Pages: 547-548 .
Authors: Kumar, Ashish;Alam, Mohammad Aftab;Visweswaran, G. S.
DOI 10.1109/VLSID.2019.00129
1

A 0.6V Retention VMIN Ultra-Low Leakage High Density 6T SRAM in 40nm CMOS Technology Using Adaptive Source Bias

Open Access
Conference Paper
Year: 2018. Volume: 2018-January , Pages: 261-265 .
Authors: Kumar, Ashish;Visweswaran, G. S.
DOI 10.1109/VLSID.2018.73
1 1

Charge-Controlled Oscillators and Their Application in Frequency Synthesis

Open Access
Article
Year: 2017. Volume: 64 , Issue: 10 , Pages: 1127-1131 .
Authors: Kaushik R.;Chatterjee S.;Visweswaran G.S.
DOI 10.1109/TCSII.2016.2563738

A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM with 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS

Open Access
Article
Year: 2017. Volume: 64 , Issue: 9 , Pages: 2438-2447 .
Authors: Grover A.;Visweswaran G.S.;Parthasarathy C.R.;Daud M.;Turgis D.;Giraud B.;Noel J.P.;Miro-Panades I.;Moritz G.;Beigne E.;Flatresse P.;Kumar P.;Azmi S.
DOI 10.1109/TCSI.2017.2705116
13 18

An effective test methodology enabling detection of weak bits in SRAMs: Case study in 28nm FDSOI

Open Access
Conference Paper
Year: 2017.
Authors: Batra N.;Gundu A.K.;Hashmi M.S.;Visweswaran G.S.;Grover A.
DOI 10.1109/ISVDAT.2016.8064868
1 2

Impact of crosstalk and process variation on capture power reduction for at-speed test

Open Access
Conference Paper
Year: 2016. Volume: 2016-May .
Authors: Piplani S.;Visweswaran G.S.;Kumar A.
DOI 10.1109/VTS.2016.7477291
1 1

Heterogeneous memory assembly exploration using a floorplan and interconnect aware framework

Open Access
Conference Paper
Year: 2016. Pages: 290-295 .
Authors: Gupta P.R.;Visweswaran G.S.;Narang G.;Grover A.
DOI 10.1109/SOCC.2016.7905494
1 2