Ministry of Education
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Dr G S Visweswaran

vidwan id: 105057
Male

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Expertise

  • Telecommunications

Publications

Total Articles 48
Books 0
Proceedings 0

Publications

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Scopus

Citations 287
h-index 9

CrossRef

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Citations 204
h-index 7
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Professional Recognition

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Bio

CAD of VLSI, Design of Digital, Analog and Mixed Signal VLSI Circuits

Personal Details

  • Male
  • Indraprastha Institute of Information Technology Delhi, Okhla Industrial Estate, Phase III, New Delhi
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Visiting Faculty Jul 2018 – Jun 2022
Indraprastha Institute of Information Technology Delhi (IIIT Delhi) | Department of Electronics and Communication Engineering

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Organisation (0)

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Co-Authors (11)

Anshul

Prof Anshul Kumar

Indian Institute of Technology Delhi

Anuj

Dr Anuj Grover

Indraprastha Institute of Information Technology Delhi (IIIT Delhi)

B.

Prof B. Bhaumik

Indian Institute of Technology Delhi

G.S.

Prof G.S. Visweswaran

N/A

Maneesha

Dr Maneesha Gupta

Netaji Subhas University of Technology

M.

Prof M. Balakrishnan

N/A

Mohammad

Dr Mohammad S. Hashmi

N/A

Preeti Ranjan

Prof Preeti Ranjan Panda

Indian Institute of Technology Delhi

Pragya

Dr Pragya Varshney

N/A

Shiv Dutt

Prof Shiv Dutt Joshi

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Shouribrata

Prof Shouribrata Chatterjee

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Scholarly Work

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Scholarly Publications

An Equalizer with Controllable Transfer Function for 6-Gb/s HDMI and 5.4-Gb/s DisplayPort Receivers in 28-nm UTBB-FDSOI

Open Access
Article
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Year: 2016. Volume: 24 , Issue: 8 , Pages: 2803-2807 .
Authors: Sahni, Paramjeet Singh;Joshi, Suresh Chandra;Gupta, Nitin;Visweswaran, Gangaikondan Subramani
DOI 10.1109/TVLSI.2016.2530680
12 12

Impact of crosstalk and process variation on capture power reduction for at-speed test

Open Access
Conference Paper
Year: 2016. Volume: 2016-May .
Authors: Piplani S.;Visweswaran G.S.;Kumar A.
DOI 10.1109/VTS.2016.7477291
1 1

A 0.5V VMIN 6T SRAM in 28nm UTBB FDSOI Technology Using Compensated WLUD Scheme with Zero Performance Loss

Open Access
Conference Paper
Year: 2016. Volume: 2016-March , Pages: 191-195 .
Authors: Kumar, Ashish;Visweswaran, G. S.;Kumar, Vinay;Saha, Kaushik
DOI 10.1109/VLSID.2016.62
5 7

A 6T-SRAM in 28nm FDSOI technology with Vmin of 0.52V using assisted read and write operation

Open Access
Conference Paper
Year: 2015.
Authors: Kumar, Ashish;Kumar, Vinay;Janardan, Dhori Kedar;Visweswaran, G. S.;Saha, Kaushik
DOI 10.1109/ICICDT.2015.7165877
1 2

Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs

Open Access
Conference Paper
Year: 2015.
Authors: Grover A.;Kumar P.;Daud M.;Visweswaran G.S.;Parthasarathy C.;Noel J.P.;Turgis D.;Giraud B.;Moritz G.
DOI 10.1109/ICICDT.2015.7165876
6 7

Low voltage error resilient SRAM using run-time error detection and correction

Open Access
Conference Paper
Year: 2015. Volume: 2015-October , Pages: 335-338 .
Authors: Kumar, Ashish;Visweswaran, G. S.;Saha, Kaushik
DOI 10.1109/ESSCIRC.2015.7313895
2 2

Switched capacitor realizations of fractional-order differentiators and integrators based on an operator with improved performance

Open Access
Article
Radioengineering. Year: 2011. Volume: 20 , Issue: 1 , Pages: 340-348 .
Authors: Varshney P.;Gupta M.;Visweswaran G.S.
9

Implementation of first and third order fractional order differentiators and integrators using switched capacitors

Open Access
Conference Paper
Year: 2011.
Authors: Varshney P.;Gupta M.;Visweswaran G.S.
DOI 10.1109/IICPE.2011.5728088
1 4