Prof G.S. Visweswaran

vidwan id: 10535

Male

6602989195

Publications

Total Articles 47

Books 0

Proceedings 0

Publications

Scopus

Citations 286

h-index 9

CrossRef

Citations 202

h-index 7

Google Scholar

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Professional Recognition

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Community & Membership

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Bio

CAD of VLSI,Design of digital,Analog and mixed signal VLSI circuits

Personal Details

Male
Department of Electrical Engineering, Indian Institute of Technology Delhi, Hauz Khas

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Adjunct Lecturer Nov -0001 – —

Indian Institute of Technology Delhi | Department of Electrical Engineering

Related Profiles

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Co-Authors (11)

Prof Anshul Kumar

Indian Institute of Technology Delhi

Dr Anuj Grover

Indraprastha Institute of Information Technology Delhi (IIIT Delhi)

Prof B. Bhaumik

Indian Institute of Technology Delhi

Dr Maneesha Gupta

Netaji Subhas University of Technology

Prof M. Balakrishnan

N/A

Dr Mohammad S. Hashmi

N/A

Prof Preeti Ranjan Panda

Indian Institute of Technology Delhi

Dr Pragya Varshney

N/A

Prof Shiv Dutt Joshi

Indian Institute of Technology Delhi

Prof Shouribrata Chatterjee

Indian Institute of Technology Delhi

Dr G S Visweswaran

N/A

Scholarly Work

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Scholarly Publications

A 0.8V V<inf>MIN</inf>ultra-low leakage high density 6T SRAM in 40nm CMOS technology using repeated-pulse wordline suppression scheme

Open Access

Conference Paper

Year: 2019. Pages: 547-548 .

Authors: Kumar, Ashish;Alam, Mohammad Aftab;Visweswaran, G. S.

10.1109/VLSID.2019.00129

A 0.6V Retention VMIN Ultra-Low Leakage High Density 6T SRAM in 40nm CMOS Technology Using Adaptive Source Bias

Open Access

Conference Paper

Year: 2018. Volume: 2018-January , Pages: 261-265 .

Authors: Kumar, Ashish;Visweswaran, G. S.

10.1109/VLSID.2018.73

Charge-Controlled Oscillators and Their Application in Frequency Synthesis

Open Access

Article

Year: 2017. Volume: 64 , Issue: 10 , Pages: 1127-1131 .

Authors: Kaushik R.;Chatterjee S.;Visweswaran G.S.

10.1109/TCSII.2016.2563738

A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM with 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS

Open Access

Article

Year: 2017. Volume: 64 , Issue: 9 , Pages: 2438-2447 .

Authors: Grover A.;Visweswaran G.S.;Parthasarathy C.R.;Daud M.;Turgis D.;Giraud B.;Noel J.P.;Miro-Panades I.;Moritz G.;Beigne E.;Flatresse P.;Kumar P.;Azmi S.

10.1109/TCSI.2017.2705116

An effective test methodology enabling detection of weak bits in SRAMs: Case study in 28nm FDSOI

Open Access

Conference Paper

Year: 2017.

Authors: Batra N.;Gundu A.K.;Hashmi M.S.;Visweswaran G.S.;Grover A.

10.1109/ISVDAT.2016.8064868

Impact of crosstalk and process variation on capture power reduction for at-speed test

Open Access

Conference Paper

Year: 2016. Volume: 2016-May .

Authors: Piplani S.;Visweswaran G.S.;Kumar A.

10.1109/VTS.2016.7477291

Heterogeneous memory assembly exploration using a floorplan and interconnect aware framework

Open Access

Conference Paper

Year: 2016. Pages: 290-295 .

Authors: Gupta P.R.;Visweswaran G.S.;Narang G.;Grover A.

10.1109/SOCC.2016.7905494

A 0.5V VMIN 6T SRAM in 28nm UTBB FDSOI Technology Using Compensated WLUD Scheme with Zero Performance Loss

Open Access

Conference Paper

Year: 2016. Volume: 2016-March , Pages: 191-195 .

Authors: Kumar, Ashish;Visweswaran, G. S.;Kumar, Vinay;Saha, Kaushik

10.1109/VLSID.2016.62

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