Ministry of Education
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Dr Rahul Shrestha

vidwan id: 113371
Male

Associate Professor, School of Computing and Electrical Engineering
Indian Institute of Technology Mandi

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Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 67
Books 0
Proceedings 0

Publications

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Scopus

Citations 611
h-index 12

CrossRef

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Citations 397
h-index 10
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Bio

VLSI Design and Circuits and Systems for Signal Processing and Wireless Communication

Personal Details

  • Male
  • Associate Professor , Indian Institute of Technology Mandi
  • Indian Institute of Technology Mandi, Kamand Campus
Ph.D
Other Institute 2014
Associate Professor Dec 2016 – Present
Indian Institute of Technology Mandi | School of Computing and Electrical Engineering

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Co-Authors (6)

Rohit Buddhiram

Dr Rohit Buddhiram Chaurasiya

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Prof Roy Paily Palathinkal

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Satinder Kumar

Dr Satinder Kumar Sharma

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Scholarly Work

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Scholarly Publications

A novel architecture for computing eigenvalues of matrix for high speed applications

Open Access
Conference Paper
Year: 2017.
Authors: Dubey S.;Shrestha R.;Chowdhury S.
DOI 10.1109/INDICON.2016.7838959
2 2

A new multi-objective hardware-software-partitioning algorithmic approach for high speed applications

Open Access
Conference Paper
Year: 2017. Volume: 711 , Pages: 62-68 .
Authors: Govil N.;Shrestha R.;Roy Chowdhury S.
DOI 10.1007/978-981-10-7470-7_7
1 2

VLSI architecture for cyclostationary feature detection based spectrum sensing for cognitive-radio wireless networks and its ASIC implementation

Open Access
Conference Paper
Year: 2016. Volume: 2016-September , Pages: 69-74 .
Authors: Murty M.;Shrestha R.
DOI 10.1109/ISVLSI.2016.12
10 13

Memory-Reduced Maximum A Posteriori Probability Decoding for High-Throughput Parallel Turbo Decoders

Open Access
Article
Year: 2016. Volume: 35 , Issue: 8 , Pages: 2832-2854 .
Authors: Shrestha R.;Paily R.
DOI 10.1007/s00034-015-0168-4
1

Design and Implementation of Area-Efficient and Low-Power Configurable Booth-Multiplier

Open Access
Conference Paper
Year: 2016. Volume: 2016-March , Pages: 599-600 .
Authors: Shrestha R.;Rastogi U.
DOI 10.1109/VLSID.2016.36
5 7

Multi-standard high-throughput and lowpower quasi-cyclic low density parity check decoder for worldwide interoperability for microwave access and wireless fidelity standards

Open Access
Article
Year: 2016. Volume: 10 , Issue: 2 , Pages: 111-120 .
Authors: Kanchetla V.;Shrestha R.;Paily R.
DOI 10.1049/iet-cds.2014.0347
7 7

High-throughput LDPC-decoder architecture using efficient comparison techniques & dynamic multi-frame processing schedule

Open Access
Article
Year: 2015. Volume: 62 , Issue: 5 , Pages: 1421-1430 .
Authors: Kumawat S.;Shrestha R.;Daga N.;Paily R.
DOI 10.1109/TCSI.2015.2403032
46

VLSI design and hardware implementation of high-speed energy-efficient logarithmic-MAP decoder

Open Access
Conference Paper
Year: 2015. Volume: 11 , Issue: 3 , Pages: 406-412 .
Authors: Shrestha R.;Paily R.P.
DOI 10.1166/jolpe.2015.1391
1 1