Ministry of Education
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Dr Rahul Shrestha

vidwan id: 113371
Male

Associate Professor, School of Computing and Electrical Engineering
Indian Institute of Technology Mandi

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Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 67
Books 0
Proceedings 0

Publications

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Scopus

Citations 611
h-index 12

CrossRef

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Citations 397
h-index 10
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Bio

VLSI Design and Circuits and Systems for Signal Processing and Wireless Communication

Personal Details

  • Male
  • Associate Professor , Indian Institute of Technology Mandi
  • Indian Institute of Technology Mandi, Kamand Campus
Ph.D
Other Institute 2014
Associate Professor Dec 2016 – Present
Indian Institute of Technology Mandi | School of Computing and Electrical Engineering

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Organisations (198+)

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Balasundaram

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Adjunct Professor

Astrid

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Visiting Faculty

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Co-Authors (6)

Rohit Buddhiram

Dr Rohit Buddhiram Chaurasiya

Indian Institute of Technology Jammu

Roy Paily

Prof Roy Paily Palathinkal

Indian Institute of Technology Guwahati

Satinder Kumar

Dr Satinder Kumar Sharma

Indian Institute of Technology Mandi

Siddhartha

Dr Siddhartha Sarma

Indian Institute of Technology Mandi

Shubhajit

Dr Shubhajit Roy Chowdhury

Indian Institute of Technology Mandi

Srikant

Dr Srikant Srinivasan

Indian Institute of Technology Mandi

Scholarly Work

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Scholarly Publications

High-throughput and high-speed polar-decoder VLSI-architecture for 5G new radio

Open Access
Conference Paper
Year: 2019. Pages: 329-334 .
Authors: Shrestha R.;Bansal P.;Srinivasan S.
DOI 10.1109/VLSID.2019.00075
6 9

Parameterized Posit Arithmetic Hardware Generator

Open Access
Conference Paper
Year: 2019. Pages: 334-341 .
Authors: Chaurasiya R.;Gustafson J.;Shrestha R.;Neudorfer J.;Nambiar S.;Niyogi K.;Merchant F.;Leupers R.
DOI 10.1109/ICCD.2018.00057
77 85

Hardware-efficient and low sensing-time VLSI-architecture of MED based spectrum sensor for cognitive radio

Open Access
Conference Paper
Year: 2019. Volume: 2019-May .
Authors: Chaurasiya R.;Shrestha R.
DOI 10.1109/ISCAS.2019.8702675
3 6

Reconfigurable VLSI-Architecture of Multi-radix Maximum-A-Posteriori Decoder for New Generation of Wireless Devices

Open Access
Conference Paper
Year: 2019. Volume: 892 , Pages: 37-48 .
Authors: Shrestha R.;Sharma A.
DOI 10.1007/978-981-13-5950-7_4

VLSI-Architecture of Radix-2/4/8 SISO Decoder for Turbo Decoding at Multiple Data-rates

Open Access
Conference Paper
Year: 2018. Volume: 2018-October , Pages: 131-136 .
Authors: Shrestha R.;Sharma A.
DOI 10.1109/VLSI-SoC.2018.8644753
6 6

Hardware implementation and VLSI design of spectrum sensor for next-generation LTE-A cognitive-radio wireless network

Open Access
Article
Year: 2018. Volume: 12 , Issue: 5 , Pages: 542-550 .
Authors: Murty M.;Shrestha R.
DOI 10.1049/iet-cds.2017.0292
12 12

Reconfigurable and Memory-Efficient Cyclostationary Spectrum Sensor for Cognitive-Radio Wireless Networks

Open Access
Article
Year: 2018. Volume: 65 , Issue: 8 , Pages: 1039-1043 .
Authors: Murty M.S.;Shrestha R.
DOI 10.1109/TCSII.2018.2790952
24 29

Hardware-Efficient and Wide-Band Frequency-Domain Energy Detector for Cognitive-Radio Wireless Network

Open Access
Conference Paper
Year: 2018. Volume: 2018-January , Pages: 277-282 .
Authors: Murty M.;Shrestha R.
DOI 10.1109/VLSID.2018.76
3 4