Ministry of Education
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Dr Rahul Shrestha

vidwan id: 113371
Male

Associate Professor, School of Computing and Electrical Engineering
Indian Institute of Technology Mandi

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Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 67
Books 0
Proceedings 0

Publications

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Scopus

Citations 611
h-index 12

CrossRef

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Citations 397
h-index 10
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Bio

VLSI Design and Circuits and Systems for Signal Processing and Wireless Communication

Personal Details

  • Male
  • Associate Professor , Indian Institute of Technology Mandi
  • Indian Institute of Technology Mandi, Kamand Campus
Ph.D
Other Institute 2014
Associate Professor Dec 2016 – Present
Indian Institute of Technology Mandi | School of Computing and Electrical Engineering

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Co-Authors (6)

Rohit Buddhiram

Dr Rohit Buddhiram Chaurasiya

Indian Institute of Technology Jammu

Roy Paily

Prof Roy Paily Palathinkal

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Satinder Kumar

Dr Satinder Kumar Sharma

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Dr Siddhartha Sarma

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Dr Shubhajit Roy Chowdhury

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Dr Srikant Srinivasan

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Scholarly Work

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Scholarly Publications

Selective register-file cache: an energy saving technique for embedded processor architecture

Open Access
Article
Design Automation for Embedded Systems. Year: 2022. Volume: 26 , Issue: 2 , Pages: 105-124 .
Authors: Gudaparthi S.;Shrestha R.
DOI 10.1007/s10617-022-09264-2
2 2

Low-Latency and Reconfigurable VLSI-Architectures for Computing Eigenvalues and Eigenvectors Using CORDIC-Based Parallel Jacobi Method

Open Access
Article
Year: 2022. Volume: 30 , Issue: 8 , Pages: 1020-1033 .
Authors: Sharma R.;Shrestha R.;Sharma S.K.
DOI 10.1109/TVLSI.2022.3170526
7 8

An Uninterrupted Processing Technique-Based High-Throughput and Energy-Efficient Hardware Accelerator for Convolutional Neural Networks

Open Access
Article
Year: 2022. Volume: 30 , Issue: 12 , Pages: 1891-1901 .
Authors: Islam M.N.;Shrestha R.;Chowdhury S.R.
DOI 10.1109/TVLSI.2022.3210963
4 7

High-Throughput VLSI Architecture for LDPC Decoder Based on Low-Latency Decoding Technique for Wireless Communication Systems

Open Access
Conference Paper
Year: 2022. Volume: 2022-July , Pages: 206-211 .
Authors: Suravi K.;Shrestha R.
DOI 10.1109/ISVLSI54635.2022.00048
1 2

A New Hardware-Efficient VLSI-Architecture of GoogLeNet CNN-Model Based Hardware Accelerator for Edge Computing Applications

Open Access
Conference Paper
Year: 2022. Volume: 2022-July , Pages: 414-417 .
Authors: Islam M.N.;Shrestha R.;Chowdhury S.R.
DOI 10.1109/ISVLSI54635.2022.00093
5 6

A New Hardware-Efficient Spectrum-Sensor VLSI Architecture for Data-Fusion-Based Cooperative Cognitive-Radio Network

Open Access
Article
Year: 2021. Volume: 29 , Issue: 4 , Pages: 760-773 .
Authors: Chaurasiya R.B.;Shrestha R.
DOI 10.1109/TVLSI.2021.3055344
16 18

Hardware-efficient ASIC implementation of eigenvalue based spectrum sensor reconfigurable-architecture for cooperative cognitive-radio network

Open Access
Conference Paper
Year: 2021. Volume: 2021-May .
Authors: Chaurasiya R.B.;Shrestha R.
DOI 10.1109/ISCAS51556.2021.9401570
7 8

Area-Efficient and Scalable Data-Fusion Based Cooperative Spectrum Sensor for Cognitive Radio

Open Access
Article
Year: 2021. Volume: 68 , Issue: 4 , Pages: 1198-1202 .
Authors: Chaurasiya R.B.;Shrestha R.
DOI 10.1109/TCSII.2020.3029874
13 12