Ministry of Education
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Dr Rohit Buddhiram Chaurasiya

vidwan id: 525791
Male

Assistant Professor, Department of Electrical Engineering
Indian Institute of Technology Jammu

Orchid Icon 0000-0003-2810-9588 Google Scholar Icon 56267125400 Researcher Icon DTO-7543-2022 Google Scholar Icon RamaYC0AAAAJ

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 15
Books 0
Proceedings 0

Publications

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Scopus

Citations 300
h-index 8

CrossRef

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Citations 248
h-index 7
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Professional Recognition

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Bio

Hardware-Friendly Algorithm, Digital VLSI Architecture, ASIC Chip Design, and FPGA Prototyping for Spectrum Sensing in Cognitive Radio Networks.

Personal Details

  • Male
  • Assistant Professor , Indian Institute of Technology Jammu
  • IIT Jammu, Jagti, Nagrota
PhD
Other Institute 2022
Assistant Professor May 2024 – Present
Indian Institute of Technology Jammu | Department of Electrical Engineering

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Co-Authors (8)

Divya Kalpesh

Divya Kalpesh Shah

Padmashree Dr D Y Patil Vidyapeeth, Mumbai

Divya Kalpesh

Divya Kalpesh Shah

Ramrao Adik Institute of Technology, Navi Mumbai

Mukesh

Dr Mukesh Patil

Padmashree Dr D Y Patil Vidyapeeth, Mumbai

Mukesh

Dr Mukesh Patil

Ramrao Adik Institute of Technology, Navi Mumbai

Rahul

Dr Rahul Shrestha

Indian Institute of Technology Mandi

Siddhartha

Dr Siddhartha Sarma

Indian Institute of Technology Mandi

Vishwesh

Dr Vishwesh Vyawahare

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Vishwesh

Dr Vishwesh Vyawahare

Ramrao Adik Institute of Technology, Navi Mumbai

Scholarly Work

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Scholarly Publications

FPGA Implementation of Resource-Efficient Cube Calculation Architecture Using Yavadunam Sutra

Open Access
Conference Paper
Year: 2025. Volume: 1210 LNEE , Pages: 171-184 .
Authors: Shukla M.;Thakur A.S.;Chaurasiya R.;Gupta D.
DOI 10.1007/978-981-97-3756-7_14

Energy-Preserving Indirect-feedback for Wireless Power Transfer: Algorithm & Hardware Architecture

Open Access
Article
IEEE Transactions on Green Communications and Networking. Year: 2025.
Authors: Sarma S.;Shrestha R.;Chaurasiya R.B.
DOI 10.1109/TGCN.2025.3552431
1

Hardware-Efficient VLSI Architecture and ASIC Implementation of GRCR-Based Cooperative Spectrum Sensor for Cognitive-Radio Network

Open Access
Article
Year: 2022. Volume: 30 , Issue: 2 , Pages: 166-176 .
Authors: Chaurasiya R.B.;Shrestha R.
DOI 10.1109/TVLSI.2021.3114859
6 6

Design and ASIC-Implementation of Hardware-Efficient Cooperative Spectrum-Sensor for Data Fusion-Based Cognitive Radio Network

Open Access
Article
IEEE Transactions on Consumer Electronics. Year: 2022. Volume: 68 , Issue: 3 , Pages: 221-235 .
Authors: Chaurasiya R.B.;Shrestha R.
DOI 10.1109/TCE.2022.3167471
9 11

Area-Efficient and Scalable Data-Fusion Based Cooperative Spectrum Sensor for Cognitive Radio

Open Access
Article
Year: 2021. Volume: 68 , Issue: 4 , Pages: 1198-1202 .
Authors: Chaurasiya R.B.;Shrestha R.
DOI 10.1109/TCSII.2020.3029874
13 12

A New Hardware-Efficient Spectrum-Sensor VLSI Architecture for Data-Fusion-Based Cooperative Cognitive-Radio Network

Open Access
Article
Year: 2021. Volume: 29 , Issue: 4 , Pages: 760-773 .
Authors: Chaurasiya R.B.;Shrestha R.
DOI 10.1109/TVLSI.2021.3055344
16 18

Hardware-efficient ASIC implementation of eigenvalue based spectrum sensor reconfigurable-architecture for cooperative cognitive-radio network

Open Access
Conference Paper
Year: 2021. Volume: 2021-May .
Authors: Chaurasiya R.B.;Shrestha R.
DOI 10.1109/ISCAS51556.2021.9401570
7 8

Fast Sensing-Time and Hardware-Efficient Eigenvalue-Based Blind Spectrum Sensors for Cognitive Radio Network

Open Access
Article
Year: 2020. Volume: 67 , Issue: 4 , Pages: 1296-1308 .
Authors: Chaurasiya R.B.;Shrestha R.
DOI 10.1109/TCSI.2019.2941762
24 26