Ministry of Education
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Dr Rohit Buddhiram Chaurasiya

vidwan id: 525791
Male

Assistant Professor, Department of Electrical Engineering
Indian Institute of Technology Jammu

Orchid Icon 0000-0003-2810-9588 Google Scholar Icon 56267125400 Researcher Icon DTO-7543-2022 Google Scholar Icon RamaYC0AAAAJ

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 15
Books 0
Proceedings 0

Publications

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Scopus

Citations 300
h-index 8

CrossRef

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Citations 248
h-index 7
Google Scholar

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Professional Recognition

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Community & Membership

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Bio

Hardware-Friendly Algorithm, Digital VLSI Architecture, ASIC Chip Design, and FPGA Prototyping for Spectrum Sensing in Cognitive Radio Networks.

Personal Details

  • Male
  • Assistant Professor , Indian Institute of Technology Jammu
  • IIT Jammu, Jagti, Nagrota
PhD
Other Institute 2022
Assistant Professor May 2024 – Present
Indian Institute of Technology Jammu | Department of Electrical Engineering

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Co-Authors (8)

Divya Kalpesh

Divya Kalpesh Shah

Padmashree Dr D Y Patil Vidyapeeth, Mumbai

Divya Kalpesh

Divya Kalpesh Shah

Ramrao Adik Institute of Technology, Navi Mumbai

Mukesh

Dr Mukesh Patil

Padmashree Dr D Y Patil Vidyapeeth, Mumbai

Mukesh

Dr Mukesh Patil

Ramrao Adik Institute of Technology, Navi Mumbai

Rahul

Dr Rahul Shrestha

Indian Institute of Technology Mandi

Siddhartha

Dr Siddhartha Sarma

Indian Institute of Technology Mandi

Vishwesh

Dr Vishwesh Vyawahare

Padmashree Dr D Y Patil Vidyapeeth, Mumbai

Vishwesh

Dr Vishwesh Vyawahare

Ramrao Adik Institute of Technology, Navi Mumbai

Scholarly Work

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Scholarly Publications

Hardware-Efficient and Fast Sensing-Time Maximum-Minimum-Eigenvalue-Based Spectrum Sensor for Cognitive Radio Network

Open Access
Article
Year: 2019. Volume: 66 , Issue: 11 , Pages: 4448-4461 .
Authors: Chaurasiya R.B.;Shrestha R.
DOI 10.1109/TCSI.2019.2921831
33 45

Parameterized Posit Arithmetic Hardware Generator

Open Access
Conference Paper
Year: 2019. Pages: 334-341 .
Authors: Chaurasiya R.;Gustafson J.;Shrestha R.;Neudorfer J.;Nambiar S.;Niyogi K.;Merchant F.;Leupers R.
DOI 10.1109/ICCD.2018.00057
77 85

Hardware-efficient and low sensing-time VLSI-architecture of MED based spectrum sensor for cognitive radio

Open Access
Conference Paper
Year: 2019. Volume: 2019-May .
Authors: Chaurasiya R.;Shrestha R.
DOI 10.1109/ISCAS.2019.8702675
3 6

FPGA implementation of fractional-order chaotic systems

Open Access
Article
Year: 2017. Volume: 78 , Pages: 245-257 .
Authors: Shah D.K.;Chaurasiya R.B.;Vyawahare V.A.;Pichhode K.;Patil M.D.
DOI 10.1016/j.aeue.2017.05.005
48 62

FPGA implementation of efficient vedic multiplier

Open Access
Conference Paper
Year: 2016. Pages: 565-570 .
Authors: Pichhode K.;Patil M.D.;Shah D.;Rohit B.C.
DOI 10.1109/INFOP.2015.7489448
6 12

Vehicle parking system implementation using CPLD

Open Access
Conference Paper
Year: 2015.
Authors: Shah D.K.;Chaurasiya Rohit B.;Sen D.;Goyal S.
DOI 10.1109/ICCICT.2015.7045668
2 2

FPGA implementation of SVPWM control technique for three phase induction motor drive using fixed point realization

Open Access
Conference Paper
Year: 2014. Pages: 93-98 .
Authors: Chaurasiya R.B.;Patil M.D.;Shah D.;Kadam A.
DOI 10.1109/CSCITA.2014.6839241
3 7