Ministry of Education
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Prof Abhisek Dixit

vidwan id: 70121
Male

Professor, Department of Electrical Engineering
Indian Institute of Technology Delhi

Google Scholar Icon 55798800800

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 124
Books 0
Proceedings 0

Publications

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Scopus

Citations 2014
h-index 23

CrossRef

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Citations 1156
h-index 16
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Professional Recognition

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Community & Membership

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Bio

Logic CMOS device design and characterization, CMOS variability, reliability and thermal-effects, Agressively scaled CMOS embedded DRAM (eDRAM) and SRAM cells, Compact device moldeing and process design kits (PDK), Modeling and characterization of Si solar-cells and modules

Personal Details

  • Male
  • Professor , Indian Institute of Technology Delhi
  • Indian Institute of Technology Delhi, Hauz Khas
Dr. Engg.
Other Institute 2007
Professor May 2021 – Present
Indian Institute of Technology Delhi | Department of Electrical Engineering
Associate Professor Oct 2013 – Nov -0001
Indian Institute of Technology Delhi | Department of Electrical Engineering

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Co-Authors (12)

Anil

Dr Anil Kottantharayil

Indian Institute of Technology Bombay

Bhaskar

Prof Bhaskar Mitra

Indian Institute of Technology Delhi

Yogesh Singh

Dr Yogesh Singh Chauhan

Indian Institute of Technology Kanpur

Manoj

Dr Manoj Kumar

CSIR-National Metallurgical Laboratory

Madhusudan

Prof Madhusudan Singh

Indian Institute of Technology Delhi

Pragya

Dr Pragya Kushwaha

Indian Institute of Technology Jodhpur

Rajan Kumar

Dr Rajan Kumar Pandey

Vellore Institute of Technology, Vellore

Ravikant

Dr Ravikant Saini

Indian Institute of Technology Jammu

Ramchandra

Dr Ramchandra Gurjar

Shri G. S. Institute of Technology & Science, Indore

Rajiv O

Dr Rajiv O Dusane

Indian Institute of Technology Bombay

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Prof V. Ramgopal Rao

Birla Institute of Technology and Science

Mohit

Dr Mohit Bajaj

Graphic Era University, Dehradun

Scholarly Work

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Scholarly Publications

Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency

Open Access
Conference Paper
Year: 2006.
Authors: Rooyackers R.;Augendre E.;Degroote B.;Collaert N.;Nackaerts A.;Dixit A.;Vandeweyer T.;Pawlak B.;Ercken M.;Kunnen E.;Dilliway G.;Leys F.;Loo R.;Jurczak M.;Biesemans S.
DOI 10.1109/IEDM.2006.346954
11 22

Reliability comparison of triple-gate versus planar SOI FETs

Open Access
Article
IEEE Transactions on Electron Devices. Year: 2006. Volume: 53 , Issue: 9 , Pages: 2351-2356 .
Authors: Crupi F.;Kaczer B.;Degraeve R.;Subramanian V.;Srinivasan P.;Simoen E.;Dixit A.;Jurczak M.;Groeseneken G.
DOI 10.1109/TED.2006.880824
44 49

GIDL (Gate-Induced Drain Leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO2/TiN FinFET devices

Open Access
Conference Paper
Year: 2005. Volume: 2005 , Pages: 725-728 .
Authors: Hoffmann T.;Doornbos G.;Ferain I.;Collaert N.;Zimmerman P.;Goodwin M.;Rooyackers R.;Kottantharayil A.;Yim Y.;Dixit A.;De Meyer K.;Jurczak M.;Biesemans S.
47

Parasitic source/drain resistance reduction in N-channel SOI MuGFETs with 15nm wide fins

Open Access
Conference Paper
Year: 2005. Volume: 2005 , Pages: 226 .
Authors: Dixit A.;Anil K.G.;Collaert N.;Rooyackers R.;Leys F.;Ferain I.;De Keersgieter A.;Hoffmann T.Y.;Loo R.;Goodwin M.;Zimmerman P.;Caymax M.;De Meyer K.;Jurczak M.;Biesemans S.
DOI 10.1109/SOI.2005.1563597
2 5

Minimization of the MuGFET contact resistance by integration of NiSi contacts on epitaxially raised source/drain regions

Open Access
Conference Paper
Year: 2005. Volume: 2005 , Pages: 445-448 .
Authors: Dixit A.;Anil K.G.;Rooyackers R.;Leys F.;Kaiser M.;Weemaes R.;Ferain I.;De Keersgieter A.;Collaert N.;Surdeanu R.;Goodwin M.;Zimmerman P.;Loo R.;Caymax M.;Jurczak M.;Biesemans S.;De Meyer K.
DOI 10.1109/ESSDER.2005.1546680
4 11

CMP-less integration of Fully Ni-Silicided Metal Gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach

Open Access
Conference Paper
Year: 2005. Volume: 2005 , Pages: 198-199 .
Authors: Anil K.G.;Verheyen P.;Collaert N.;Dixit A.;Kaczer B.;Snow J.;Vos R.;Locorotondo S.;Degroote B.;Shi X.;Rooyackers R.;Mannaert G.;Brus S.;Yim Y.S.;Lauwers A.;Goodwin M.;Kittl J.A.;Van Dal M.;Richard O.;Veloso A.;Kubicek S.;Beckx S.;Boullart W.;De Meyer K.;A
DOI 10.1109/.2005.1469266
8 21

Towards optimally shaped fins in p-channel tri-gate FETs: Can fin height be reduced further?

Open Access
Conference Paper
Year: 2005. Pages: 112-113 .
Authors: Dixit A.;Anil K.G.;Mercha A.;Collaert R.;Brus S.;Richard O.;Rooyackers R.;Goodwin M.;Jurczak M.;De Meyer K.
DOI 10.1109/VTSA.2005.1497101
4 6

NMOS and PMOS triple gate devices with mid-gap metal gate on oxynitride and Hf based gate dielectrics

Open Access
Conference Paper
Year: 2005. Pages: 136-137 .
Authors: Henson K.;Collaert N.;Demand M.;Goodwin M.;Brus S.;Rooyackers R.;Van Ammel A.;Degroote B.;Ercken M.;Baerts C.;Anil K.G.;Dixit A.;Beckx S.;Schram T.;Deweerd W.;Boullart W.;Schaekers M.;De Gendt S.;De Meyer K.;Yim Y.;Hooker J.C.;Jurczak M.;Biesemans S.
9