Ministry of Education
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Dr Sreehari Veeramachaneni

vidwan id: 346648
Male

Associate Professor, Electronics and Communication Engineering
Goka Raju Ranga Raju Institute of Engineering & Technology

Orchid Icon 0000-0001-7744-4580 Google Scholar Icon 21835132600 Researcher Icon AAT-7782-2021 Google Scholar Icon 1Mkl5QoAAAAJ

Expertise

  • Telecommunications

Publications

Total Articles 44
Books 0
Proceedings 0

Publications

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Scopus

Citations 73
h-index 5

CrossRef

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Citations 58
h-index 5
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Professional Recognition

2006

Intel India Research Challenge -Winner

INTEL
2007

Cadence Design Contest-Winner

Cadence

Community & Membership

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ACM

2021
ACM Senior Member

IEEE

2019
IEEE Senior Member

Bio

Arithmetic Circuits, Approximate Computing, Hardware Security Memory Design, Data Converters, Analog VLSI Design Low Power Design

Personal Details

  • Male
  • Associate Professor , Goka Raju Ranga Raju Institute of Engineering & Technology
  • Department of Electronics and Communication Engineering,Gokaraju Rangaraju Institute of Engineering and Technology
Ph.D
Other Institute 2015
Associate Professor Aug 2016 – Present
Goka Raju Ranga Raju Institute of Engineering & Technology | Electronics and Communication Engineering

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Organisations (364+)

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Dr B Ramakrishna Reddy

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Dr B Sankara Babu

Head of the Department

B Ch

Prof B Ch Nookaraju

Associate Professor

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Dr Butchi Raju Katari

Dean

Narendra

Mr Narendra Achari

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Ravi Kiran

Mr Ravi Kiran Bhamidipati

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Dr Ayyem Pillai V

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Hema Chandra

Dr Hema Chandra Rao

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Aruna

Aruna Kavuru

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Co-Authors (12)

Arun Vignesh

Dr Arun Vignesh Natarajan

Goka Raju Ranga Raju Institute of Engineering & Technology

Naresh Kumar

Mr Naresh Kumar Koppala

Gayatri Vidya Parishad College of Engineering, Visakhapatnam

Dola Gobinda

Dr Dola Gobinda Padhan

Goka Raju Ranga Raju Institute of Engineering & Technology

Bhaskara Rao

Dr Bhaskara Rao Jammu

Gayatri Vidya Parishad College of Engineering, Visakhapatnam

Jaganmohan

Dr Jaganmohan Jonnalagadda

Birla Institute of Technology and Science

Kumaravel

Dr Kumaravel S

Vellore Institute of Technology, Vellore

Saranya

Ms Saranya K

Assistant Professor - Senior Scale

Pavankumar

Dr Pavankumar Bikki

Padmasri Dr. B.V Raju Institute of Technology

Shilpa

Dr Shilpa Bagade

Vardaman College of Engineering, Rangareddy

Sireesha

Sireesha Amaraneni

Vallurupalli Nageswara Rao Vignana Jyothi Institute of Engineering and Technology

Suresh Kumar

Dr Suresh Kumar Tummala

Anurag Engineering College (2nd Shift Polytechnic) (Id: S-16567)

Syed Ershad

Dr Syed Ershad Ahmed

Birla Institute of Technology and Science

Scholarly Work

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Scholarly Publications

Novel Approximate 4:2 Compressor for Multiplier Design

Open Access
Conference Paper
Year: 2023. Volume: 962 , Pages: 65-72 .
Authors: Hemanth Krishna L.;Bhaskara Rao J.;Ayesha S.K.;Veeramachaneni S.;Noor Mahammad S.K.
DOI 10.1007/978-981-19-6780-1_6

Energy Efficient Approximate Floating Point Divider

Open Access
Conference Paper
Year: 2023.
Authors: Nadh J.N.;Ayesha S.K.;Veeramachaneni S.;Noor Mahammad S.K.
DOI 10.1109/IC2E357697.2023.10262554

Preferential fault-tolerance multiplier design to mitigate soft errors in FPGAs

Open Access
Article
Year: 2023. Volume: 93 .
Authors: Sakali R.K.;Veeramachaneni S.;Mahammad Sk N.
DOI 10.1016/j.vlsi.2023.102068

Efficient design and analysis of secure CMOS logic through logic encryption

Open Access
Article
Scientific Reports. Year: 2023. Volume: 13 , Issue: 1 .
Authors: Chandra S.S.;Kannan R.J.;Balaji B.S.;Veeramachaneni S.;Noor Mahammad S.
DOI 10.1038/s41598-023-28007-2
3 4

Optimized Fault-Tolerant Adder Design Using Error Analysis

Open Access
Article
Journal of Circuits, Systems and Computers. Year: 2023. Volume: 32 , Issue: 6 .
Authors: Raghavendra Kumar S.;Balasubramanian P.;Reddy R.;Veeramachaneni S.;Sk N.M.
DOI 10.1142/S0218126623500913
2

Modified priority encoder based hardware efficient N-bit comparator

Open Access
Article
International Journal of Electronics Letters. Year: 2023. Volume: 11 , Issue: 4 , Pages: 426-438 .
Authors: Bodasingi N.;Varasala K.;Saladi S.;Chalumuri A.N.;Jammu B.R.;Veeramachaneni S.
DOI 10.1080/21681724.2022.2117848

Power Efficient Approximate Divider Architecture for Error Resilient Applications

Open Access
Conference Paper
Year: 2022.
Authors: Shriram A.;Tiwari A.;Anil Kumar U.;Ravi Teja Karri B.;Veeramachaneni S.;Ershad Ahmed S.
DOI 10.1109/CICT56698.2022.9997960
1 3

Logic Locking Designs at Transistor Level for Full Adders

Open Access
Conference Paper
Year: 2022. Pages: 289-292 .
Authors: Kolla S.;Ayesha S.K.;Veeramachaneni S.;Noor Mahammad S.K.
DOI 10.1109/iSES54909.2022.00065