Ministry of Education
Vidvan Image

Ms Saranya K

vidwan id: 310125
Female

Assistant Professor - Senior Scale,

Google Scholar Icon 57215754825 Google Scholar Icon u2QFZX0AAAAJ

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 6
Books 0
Proceedings 0

Publications

No publication activity to display at the moment.

Scopus

Citations 38
h-index 3

CrossRef

CrossRef Icon
Citations 20
h-index 2
Google Scholar

Loading Scholar statistics...

Professional Recognition

No Data Found

There is currently nothing to display here.

Community & Membership

No Data Found

There is currently nothing to display here.

ISTE

2010
Life Time Member

Bio

VLSI,ASIC Design,Image Cryptography

Personal Details

  • Female
  • Assistant Professor - Senior Scale
  • Dr Mahalingam College of Engineering and Technology, Makkinampatti (POST), Udumalai Road, Pollachi
Ph.D
Anna University 2022
Assistant Professor - Senior Scale Jun 2010 – Present
Unknown Organization

Related Profiles

Experts (19623+)

View All
Pragati

Ms Pragati Mishra

Assistant Professor

Sridhar

Dr Sridhar Sekar

Assistant Professor

DEEPAK

Mr DEEPAK B N

N/A

Md

Dr Md Nadeem M

Assistant Professor

Rashmi

Rashmi Chandra

Assistant Professor

Anjali

Dr Anjali Jadhav

Doctor

Abhishek

Mr Abhishek Shukla

Assistant Professor (Grade-I)

N

Dr N PRAKASH

Assistant Professor

Mrinmoy

Mr Mrinmoy Sadhukhan

Research Scholar

Haranath

Mr Haranath Rakshit

Junior Research Fellow

Organisation (0)

no data

Co-Authors (2)

Sreehari

Dr Sreehari Veeramachaneni

Goka Raju Ranga Raju Institute of Engineering & Technology

Vijeyakumar

Dr Vijeyakumar K N

Professor

Scholarly Work

No Data Found

There is currently nothing to display here.

No Data Found

There is currently nothing to display here.

No Data Found

There is currently nothing to display here.

Scholarly Publications

A New Approximate 4-2 Compressor using Merged Sum and Carry

Open Access
Article
Year: 2022.
Authors: Jyothi C.;Saranya K.;Jammu B.R.;Veeramachaneni S.;Mahammad S.N.
DOI 10.1007/s10836-022-06019-6
1

A Low Area FPGA Implementation of Reversible Gate Encryption with Heterogeneous Key Generation

Open Access
Article
Circuits, Systems, and Signal Processing. Year: 2021. Volume: 40 , Issue: 8 , Pages: 3836-3865 .
Authors: Saranya K.;Vijeyakumar K.N.
DOI 10.1007/s00034-021-01649-1
4

A Novel n-Decimal Reversible Radix Binary-Coded Decimal Multiplier Using Radix Encoding Scheme

Open Access
Article
Circuits, Systems, and Signal Processing. Year: 2021. Volume: 40 , Issue: 4 , Pages: 1743-1761 .
Authors: Saranya K.;Vijeyakumar K.N.
DOI 10.1007/s00034-020-01549-w
1 2

Area Efficient Approximate 4-2 Compressor for Multiplier Design

Open Access
Conference Paper
Year: 2020. Pages: 231-235 .
Authors: Jyothi C.;Gayathri K.;Karunamurthi S.;Veeramachaneni S.;Noor Mahammad S.
DOI 10.1109/INDISCON50162.2020.00055
2 2

VLSI implementation of reversible logic gates cryptography with LFSR key

Open Access
Article
Microprocessors and Microsystems. Year: 2019. Volume: 69 , Pages: 68-78 .
Authors: Karunamurthi S.;Krishnasamy Natarajan V.
DOI 10.1016/j.micpro.2019.05.015
15 25

ASIC implementation of 64-bit comparator using reversible logic

Open Access
Conference Paper
Year: 2017. Volume: 2018-January , Pages: 1-3 .
Authors: Saranya T.;Mallikarjunan P.;Rajadurai M.;Saranya K.
DOI 10.1109/ICIIECS.2017.8275855
2 4