Ministry of Education
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Prof Harsupreet Kaur

vidwan id: 283469
Female

Associate Professor, Department of Electronic Science
University of Delhi

Google Scholar Icon 13205623400

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 112
Books 0
Proceedings 0

Publications

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Scopus

Citations 445
h-index 12

CrossRef

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Citations 349
h-index 10
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Professional Recognition

2008

Young Scientist Award

International Union of Radio Science (Union Radio-Scientifique Internationale)

Community & Membership

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IEEE EDS Delhi Chapter

2019
EXCOM member

IEEE EDS Delhi Chapter

2019
Secretary

IEEE USA

2018
Senior member

Semiconductor Society of India

2013
Life member

Electronic Devices Society, USA

2012
Senior member

Bio

Electrical and Electronic Engineering

Personal Details

  • Female
  • Associate Professor , University of Delhi
  • University of Delhi, Benito Juarez Marg, South Campus, South Moti Bagh
Ph.D
University of Delhi 2009
Associate Professor Apr 2013 – Present
University of Delhi | Department of Electronic Science

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Scholarly Work

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Scholarly Publications

Negative Capacitance Germanium-Double Gate FET- A Novel Device Concept for Ultra Low Voltage/Low Power Applications

Open Access
Conference Paper
Year: 2018. Pages: 293-296 .
Authors: Bansal M.;Kaur H.
DOI 10.1109/CETIC4.2018.8531053

Impact of ferroelectric material properties on device characteristics of ferroelectric Ge0.97Sn0.03 Double Gate FET (FEGeSnDGFET)

Open Access
Conference Paper
Year: 2018.
Authors: Bansal M.;Kaur H.
DOI 10.1109/IMaRC.2018.8877157

Dual Material Gate-Gate Stack-Elliptical Gate All Around (DMG-GS-EG) MOSFET - A Novel Device Concept for Improved Performance

Open Access
Conference Paper
Year: 2018.
Authors: Pandey P.;Puri P.;Kaur H.
DOI 10.1109/ICAECC.2018.8479447

High temperature performance of Si: HfO2 based long channel double gate ferroelectric junctionless transistors

Open Access
article
Superlattices and Microstructures. Year: 2017. Volume: 103 , Pages: 78--84 .
Authors: Mehta, Hema and Kaur, Harsupreet

Analytical model to study temperature dependent Negative Capacitance effect on long channel Double Gate Ferroelectric Junctionless Transistor

Open Access
Conference Paper
Year: 2017.
Authors: Mehta H.;Kaur H.
DOI 10.1109/APMC.2016.7931309

Analytical model to study the impact of ferroelectric materials SBT/PZT on elliptical gate all around junctionless transistor

Open Access
Conference Paper
Year: 2017.
Authors: Mehta H.;Kaur H.
DOI 10.1109/TENCONSpring.2017.8070038
1 1

Analytical drain current model to study the impact of negative capacitance phenomenon in Symmetric Double Gate Junctionless Transistor

Open Access
Conference Paper
Year: 2017. Pages: 1790-1793 .
Authors: Mehta H.;Kaur H.
DOI 10.1109/TENCON.2016.7848328

Impact of interface layer and metal workfunction on device performance of ferroelectric junctionless cylindrical surrounding gate transistors

Open Access
Article
Superlattices and Microstructures. Year: 2017. Volume: 111 , Pages: 194-205 .
Authors: Mehta H.;Kaur H.
DOI 10.1016/j.spmi.2017.06.032
4 3