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Dr Jai Gopal Pandey

vidwan id: 215916
Male

Principal Scientist, Societal Electronics Group
Central Electronics Enginnering Research Institute

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 33
Books 0
Proceedings 0

Publications

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Scopus

Citations 206
h-index 9

CrossRef

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Citations 124
h-index 6
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Professional Recognition

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Community & Membership

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Bio

VLSI Design, High-Performance Architectures, System-on-Chips,Cryptography, Hardware Security, FPGA-based Designs

Personal Details

  • Male
  • Principal Scientist , Central Electronics Enginnering Research Institute
  • Central Electronics Engineering Research Institute, Pilani
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Principal Scientist Mar 2020 – Present
Central Electronics Enginnering Research Institute | Societal Electronics Group

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Co-Authors (8)

Abhijit

Dr Abhijit Karmakar

Indian Institute of Technology Jodhpur

Ambika Prasad

Dr Ambika Prasad Shah

Indian Institute of Technology Jammu

Chandra

Dr Chandra Shekhar

Birla Institute of Technology and Science

Chandra

Dr Chandra Shekhar

Birla Institute of Technology and Science

Gaurav

Dr Gaurav Dhiman

DIT University

S.

Dr S. Gurunarayanan

Birla Institute of Technology and Science

Dr S Sheeba

Dr Dr S Sheeba Rani

Sri Eshwar College of Engineering

Santosh Kumar

Dr Santosh Kumar Vishvakarma

Indian Institute of Technology Indore

Scholarly Work

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Scholarly Publications

Utilizing manufacturing variations to design a tri-state flip-flop PUF for IoT security applications

Open Access
Article
Authors: Khan S.;Shah A.P.;Chouhan S.S.;Rani S.;Gupta N.;Pandey J.G.;Vishvakarma S.K.

A symmetric D flip-flop based PUF with improved uniqueness

Open Access
Article
Authors: Khan S.;Shah A.P.;Chouhan S.S.;Gupta N.;Pandey J.G.;Vishvakarma S.K.

A Unified Architecture for AES/PRESENT Ciphers and its Usage in an SoC Environment

Open Access
Conference Paper
Authors: Pandey J.G.;Gupta S.;Karmakar A.

An ultra-low power, reconfigurable, aging resilient RO PUF for IoT applications

Open Access
Article
Authors: Khan S.;Shah A.P.;Gupta N.;Chouhan S.S.;Pandey J.G.;Vishvakarma S.K.

A Novel Design of SRAM Using Memristors at 45 nm Technology

Open Access
Conference Paper

Unsupervised image thresholding: hardware architecture and its usage for FPGA-SoC platform

Open Access
journal-article

A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations

Open Access
Conference Paper
Authors: Pandey J.G.;Goel T.;Nayak M.;Mitharwal C.;Khan S.;Vishvakarma S.K.;Karmakar A.;Singh R.

An Ultra Low Power AES Architecture for IoT

Open Access
Conference Paper
Authors: Khan S.;Gupta N.;Raut G.;Rajput G.;Pandey J.G.;Vishvakarma S.K.