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Dr Nilesh Patidar

vidwan id: 179252
Male

Assistant Professor, Department of Electrical and Electronics Engineering
Shri Vaishnav Vidyapeeth Vishwavidyalaya

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 14
Books 0
Proceedings 0

Publications

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Scopus

Citations 20
h-index 2

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Professional Recognition

2013

Best Paper Award

Trans-stellar Journals (TJPRC)
2020

TBT-2020

e-Yantra, IIT Bombay
2020

Top in 5% Topper (Introduction to Embedded System Design)

NPTEL Online Certification
2023

Top 1% Topper (AIR-1) in FDP on Digital System Design

NPTEL
2023

NPTEL Discipline Star Award in Electrical and Electronics Engineering

NPTEL

Community & Membership

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IAENG

2016
Associate Member

IRED

2016
Associate Member

Bio

Dr. Nilesh Patidar is Currently Working as An assistant Professor In the department of Electronics and Communication Engineering At Shri Vaishnav Institute of Technology and Science, Indore. He received the Degree of Bachelor of Engineering in Electronics and Communication Engineering from JIT, Borawan (M.P.), in 2009, and the Master of Engineering in Embedded System and VLSI Design from SVITS, Indore in 2013. He completes Ph.D. under the faculty of Electronics Engineering in 2023.

Personal Details

  • Male
  • Assistant Professor , Shri Vaishnav Vidyapeeth Vishwavidyalaya
  • Shri Vaishnav Vidyapeeth Vishwavidyalaya, Ujjain Road
Ph.D.
Shri Vaishnav Vidyapeeth Vishwavidyalaya 2023
M.E.
Shri Vaishnav Institute of Technology and Science 2013
B.E.
Other Institute 2009
Assistant Professor Jul 2016 – Present
Shri Vaishnav Vidyapeeth Vishwavidyalaya | Department of Electrical and Electronics Engineering
Assistant Professor Aug 2013 – Jun 2016
Shri Vaishnav Institute of Technology and Science

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Co-Authors (3)

Mukesh

Dr Mukesh Patidar

Indore Institute of Science & Technology (II), Pithampur Iim, Rau, Indore - 453331

Surendra Kumar

Dr Surendra Kumar Shukla

SVKMs NMIMS Mukesh Patel School of Technology Management & Engineering

Scholarly Work

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Scholarly Publications

Design and implementation of 16-bit arithmetic logic unit using quantum dot cellular automata (QCA) technique

Open Access
article
Authors: Rashmi Pandey, Namit gupta, Nilesh Patidar

8-Bit Arithmetic Logic Unit Implementation in Quantum-dot Cellular Automata (QCA)

Open Access
inproceedings
Authors: Namit Gupta, Nilesh Patidar, K.K. Choudhary, Sumant Katiyal

Design of 1 - Bit Reversible ALU Using Proposed NN Gate and DKG Gate and its Implementation in Quantum - Dot Cellular Automata

Open Access
inproceedings
Authors: Namit Gupta, Nilesh Patidar, Amita Khabia, Kamal Choudhary, Sumant K atiyal

A Novel 4-Bit Arithmetic Logic Unit Implementation In Quantum-Dot Cellular Automata

Open Access
article
Authors: Nilesh Patidar, Namit Gupta, Amita Khabia, Sumant Katiyal and K.K. Choudhary

Design of hybrid adder-subtractor (HAS) using reversible logic gates in QCA

Open Access
article
Authors: Namit Gupta, Nilesh Patidar, Sumant Katiyal, K. K. Choudhary

Design of one bit arithmetic logic unit (ALU) in QCA

Open Access
article
Authors: Namit Gupta, S. Shrivastava, Nilesh Patidar, Sumant Katiyal, K K Choudhary