Ministry of Education
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Dr Vanita Agarwal

vidwan id: 68619
Female

Assistant Professor, Department of Electronics and Telecommunication
COEP Technological University (formerly College of Engineering, Pune)

Orchid Icon 0000-0001-9053-2577 Google Scholar Icon 57204101759 Researcher Icon T-8531-2019 Google Scholar Icon 6zeCjn0AAAAJ

Expertise

  • Computer Science Hardware and Architecture

Publications

Total Articles 31
Books 0
Proceedings 0

Publications

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Scopus

Citations 14
h-index 3

CrossRef

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Citations 32
h-index 3
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Professional Recognition

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Community & Membership

2022

International Conference on Signal and Information Processing 2022

Tutorial Chair

IEI

2021
Life Member

IEEE

2017
Member

Bio

RTL Design and Verification, Processor Design, Digital Circuit Design, Artificial Intelligence, Hardware Security, Semiconductor Devices

Personal Details

  • Female
  • Assistant Professor , COEP Technological University (formerly College of Engineering, Pune)
  • COEP Technological University, Wellesley Road, Shivajinagar
PhD
Savitribai Phule Pune University 2020
MTECH
Other Institute 2010
Assistant Professor Jan 2011 – Present
COEP Technological University (formerly College of Engineering, Pune) | Department of Electronics and Telecommunication
Research Assistant May 2006 – Dec 2008
Indian Institute of Technology Bombay

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Co-Authors (2)

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COEP Technological University (formerly College of Engineering, Pune)

Scholarly Work

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Scholarly Publications

Performance Simulation of a Traffic Sign Recognition based Neural Network on Cadence

Open Access
article
Year: 2022. Pages: 35--42 .
Authors: Patil, Ninad and Agarwal, Vanita

Implementation of Rule Based Testing for Digital Circuits Using Inductive Logic Programming

Open Access
ARTICLE
Year: 2022. Volume: 311 , Pages: 121-134 .
Authors: Kishan Varma, S. and Agarwal, V. and Chandak, A.
DOI 10.1007/978-981-16-5529-6_10

Performance Simulation of a Traffic Sign Recognition based Neural Network on Cadence’s Tensilica Vision P6 DSP using Xtensa Xplorer IDE

Open Access
ARTICLE
WSEAS TRANSACTIONS ON COMPUTER RESEARCH. Year: 2022. Volume: 10 , Pages: 35-42 .
Authors: Patil, N. and Agarwal, V.
DOI 10.37394/232018.2022.10.5

Design and Simulation of Band 40 RF SAW Ladder-Type Filter

Open Access
inproceedings
Year: 2022. Pages: 53--56 .
Authors: Devaskar, Aditya Ravindra and Agarwal, Vanita and Kulkarni, Vinay

HLS Implementation of Quantum Shor’s Algorithm Using Matrix Pruning

Open Access
inproceedings
Year: 2022. Pages: 1--4 .
Authors: Wani, Juhi and Allamsetty, Tarun Kumar and Gherde, Rushikesh and Agarwal, Vanita

Study of Energy and Power Consumption of Rough Set Theory unit on FPGA

Open Access
inproceedings
Year: 2022. Pages: 1--6 .
Authors: Deshmukh, Apurva and Agarwal, Vanita and Ingale, Vaishali

Design and Simulation of GPS (1.56-1.61 GHz) RF Lattice and Ladder Type SAW Filter

Open Access
inproceedings
Year: 2022. Pages: 1--6 .
Authors: Waghmare, Samadhan S and Agarwal, Vanita and Kulkarni, Vinay

HLS Implementation of Quantum Shor 's Algorithm Using Matrix Pruning

Open Access
CONFERENCE
Year: 2022.
Authors: Wani, J. and Allamsetty, T.K. and Gherde, R. and Agarwal, V.
DOI 10.1109/ICAECT54875.2022.9807860