Dr Vanita Agarwal

Female

Assistant Professor, Department of Electronics and Telecommunication
COEP Technological University (formerly College of Engineering, Pune)

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Expertise

Computer Science Hardware and Architecture

Publications

Total Articles 31

Books 0

Proceedings 0

Publications

Scopus

Citations 14

h-index 3

CrossRef

Citations 32

h-index 3

Google Scholar

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Professional Recognition

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Community & Membership

2022

International Conference on Signal and Information Processing 2022

Tutorial Chair

IEI

2021

Life Member

IEEE

2017

Member

Bio

RTL Design and Verification, Processor Design, Digital Circuit Design, Artificial Intelligence, Hardware Security, Semiconductor Devices

Personal Details

Female
Assistant Professor , COEP Technological University (formerly College of Engineering, Pune)
COEP Technological University, Wellesley Road, Shivajinagar

PhD

Savitribai Phule Pune University 2020

MTECH

Other Institute 2010

Assistant Professor Jan 2011 – Present

COEP Technological University (formerly College of Engineering, Pune) | Department of Electronics and Telecommunication

Research Assistant May 2006 – Dec 2008

Indian Institute of Technology Bombay

Related Profiles

Experts (785+)

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Assistant Professor

Assistant Professor

N/A

Assistant Professor

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Doctor

Assistant Professor (Grade-I)

Dr N PRAKASH

Assistant Professor

Mr Mrinmoy Sadhukhan

Research Scholar

Mr Haranath Rakshit

Junior Research Fellow

Organisations (209+)

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Assistant Professor

Assistant Professor

Adjunct Lecturer

Assistant Professor

Assistant Professor

Assistant Professor

Assistant Archaeologist

Dr Bharatkumar Ahuja

Director

Ms Shivnanda Bhavikatti

Associate Professor

Dr Balkrishna Dawari

Associate Professor

Co-Authors (2)

Dr Rajendrakumar Patil

N/A

Dr Vaishali Ingale

COEP Technological University (formerly College of Engineering, Pune)

Scholarly Work

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Scholarly Publications

Design of 128-Bit of Magnitude Comparator Using DPL Logic

Open Access

Conference Paper

Year: 2018.

Authors: Patil R.;Agarwal V.

10.1109/ICCUBEA.2017.8463922

Design of suitable Magnitude Comparator Architecture for Big Data Analytics

Open Access

article

International Journal on Recent and Innovation Trends in Computing and Communication. Year: 2017. Volume: 5 , Pages: PP--486 .

Authors: Chougale, Reshma B. and Agarwal, Vanita

Standard Cell extraction scheme for improving timing model accuracy

Open Access

inproceedings

Year: 2016.

Authors: Chingudi, Pravin and Agarwal, Vanita

Interface circuit design for capacitive sensing transducer in 0.18um CMOS technology

Open Access

inproceedings

Year: 2016.

Authors: Ambure, Shankar and Agarwal, Vanita

Timing closure and leakage optimization using MCMM optimization

Open Access

inproceedings

Year: 2016.

Authors: Khandekar, Nilesh S and Agarwal, Vanita

Design Security and Reconfigurable VLSI designs for strategic IP development

Open Access

article

Year: 2015. Volume: 2 .

Authors: Agarwal, Vanita and Saraf, Ashok and Patil, R A

A Novel Approach for False Minutiae Removal and Minutiae Based Fingerprint Matching

Open Access

inproceedings

Year: 2012.

Authors: Manvar, Jay P. and Radadiya, Bhavesh D. and Agarwal, Vanita and Sutaone, Mukul S.

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