Dr Sambhu Nath Pradhan

vidwan id: 59668

Male

Professor,
National Institute of Technology Agartala

0000-0002-5461-6535 Google Scholar Icon

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ABC-8107-2020 Google Scholar Icon

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Expertise

Electrical and Electronic Engineering

Publications

Total Articles 95

Books 0

Proceedings 0

Publications

Scopus

Citations 417

h-index 11

CrossRef

Citations 278

h-index 9

Google Scholar

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Professional Recognition

2013

Young Scientist Award

DST

Community & Membership

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Bio

Low Power and Thermal Aware VLSI Design, Synthesis and Testing. Aging Analysis of VLSI Circuits, Hardware Implimentation of Signal Processing Algorithms. Design and Development of Air Quality Monitoring System.

Personal Details

Male
Professor , National Institute of Technology Agartala
National Institute of Technology, Agartala P.O.: NIT Agartala Barjala, Jirania, TRIPURA (W)

Ph.D

Indian Institute of Technology Kharagpur 2010

M.E

Bengal Engineering and Science University 2004

B.Tech

Other Institute 2002

Professor Feb 2024 – Present

National Institute of Technology Agartala

Associate Professor Feb 2019 – Feb 2024

National Institute of Technology Agartala | Department of Electronics and Communication Engineering

Assistant Professor May 2010 – Feb 2019

National Institute of Technology Agartala

Related Profiles

Experts (19623+)

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Assistant Professor

Assistant Professor

N/A

Assistant Professor

Assistant Professor

Doctor

Assistant Professor (Grade-I)

Dr N PRAKASH

Assistant Professor

Mr Mrinmoy Sadhukhan

Research Scholar

Mr Haranath Rakshit

Junior Research Fellow

Organisations (168+)

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Dr Baby Bhattacharya

Associate Professor

Dr Arup Ratan Bhowmik

Assistant Professor

Assistant Professor

Professor

Assistant Professor

Assistant Professor

Associate Professor

Assistant Professor (Grade-I)

Dr Biswanath Bhunia

Assistant Professor

Dr Pritam Das

Associate Professor

Co-Authors (11)

Dr Apangshu Das

National Institute of Technology Agartala

Dr Ashim Saha

National Institute of Technology Agartala

Prof Bhargab Bikram Bhattacharya

Indian Statistical Institute, Kolkata

Dr Bikram Paul

Indian Institute of Technology Mandi

Dr Bidyut K Bhattacharyya

N/A

Dr Biswajit Paul

National Institute of Technology Agartala

Dr Kanchan Manna

Birla Institute of Technology and Science

Dr Kaushik Das

National Institute of Technology Jamshedpur

Dr Mitra Barun Sarkar

National Institute of Technology Agartala

Prof Santanu Chattopadhyay

Indian Institute of Technology Kharagpur

Mr Somnath Roy Choudhury

National Institute of Technology Agartala

Scholarly Work

DESIGN AND DEVELOPMENT OF HIGH DATA RATE DEMODULATOR

Funding Agency: ISRO

Principal Investigator

13 Lakhs

2019 - 2021

Completed

SMDP-C2SD

Funding Agency: Ministry of Electronics and Information Technology

Chief Investigator

68 Lakhs

2014 - 2021

Completed

THERMAL AWARE LOGIC SYNTHESIS

Funding Agency: DeitY

Principle Investigator

23.10 Lakhs

2013 - 2016

Completed

LOW POWER VLSI CIRCUIT DESIGN

Funding Agency: AICTE

Principle Investigator

16.00 Lakhs

2012 - 2014

Completed

MODERNISATION OF AUDIO VIDEO LABORATORY

Funding Agency: AICTE

Chief Coordinator

10 Lakhs

2012 - 2013

Completed

SOME TECHNIQUES TO REDUCE LEAKAGE OF LOGIC CIRCUITS

University NIT AGARTALA

Year 2014

POWER AND THERMAL AWARE CIRCUIT SYNTHESIS USING GENETIC ALGORITHM

University NIT Agartala

Year 2017

STUDIES OF SOFT COMPUTING TECHNIQUES FOR FACIAL EXPRESSION RECOGNITION

University NIT Agartala

Year 2017

SOME STUDIES ON POWER AND NOISE REDUCTION OF POWER GATING CIRCUIT

University NIT Agartala

Year 2017

STUDY ON POWER SUPPLY NOISE AND CLOCK JITTER OF INTEGRATED CIRCUIT

University NIT Agartala

Year 2018

LOW POWER TECHNIQUES FOR INTEGRATED CIRCUITS BASED ON DYNAMICALLY CONTROLLED CLOCK AND POWER GATING

University NIT Agartala

Year 2018

POWER AND TEMPERATURE AWARE CIRCUIT TESTING

University NIT Agartala

Year 2020

THERMAL AWARE LOGIC SYNTHESIS

University NIT Agartala

Year 2021

SOME TECHNIQUES TO REDUCE POWER CONSUMPTION OF NETWORK-ON-CHIP ROUTER

University NIT Agartala

Year 2021

TIME EFFICIENT THERMAL AWARE DESIGN AUTOMATION FOR MACROCELL FLOORPLAN AND GATE ARRAY PLACEMENT

University NIT Agartala

Year 2022

SOME APPROACHES TO REDUCE THE BIAS TEMPERATURE INSTABILITY RELATED AGING DEGRADATION OF LOGIC CIRCUITS

University NIT Agartala

Year 2023

Efficient Hardware Realizations of Empirical Mode Decomposition and Some Other Related Algorithms for Signal Processing in Real-Time

University NIT Agartala

Year 2023

Growth of Zero-dimensional (0D) Carbon Nanomaterial Sensitized TiO2 Nanorod Photoanodes for Photoelectrochemical Solar Energy Conversion

University National Institute of Technology, Agartala

Year 2022

PCB DESIGN OF PORTABLE AIR QUALITY MONITORING SYSTEM WITH ENHANCED BATTERY LIFE

S. N. Pradhan

K. D. Purkayastha

D. Nath

V. K. Sing and

B. Debbarma

Engineering and Technology Application No. : 202031038999 Filed : 09-09-2020

Published : 11-03-2022 Published

Scholarly Publications

Thermal-Aware Partitioning and Encoding of Power-Gated FSM

Open Access

Article

Year: 2019. Volume: 28 , Issue: 9 .

Authors: Choudhury P.;Manna K.;Rai V.;Pradhan S.

10.1142/S0218126619501445

Low-power FSM synthesis based on automated power and clock gating technique

Open Access

Article

Year: 2019. Volume: 28 , Issue: 5 .

Authors: Nag A.;Das S.;Pradhan S.

10.1142/S0218126619200032

Power Supply Noise Reduction of Multicore CPU by Staggering Current and Variable Clock Frequency

Open Access

Article

Year: 2018. Volume: 8 , Issue: 5 , Pages: 875-882 .

Authors: Bhowmik S.;Pradhan S.;Bhattacharyya B.

10.1109/TCPMT.2018.2803139

Facial expression recognition based on eigenspaces and principle component analysis

Open Access

Conference Paper

International Journal of Computational Vision and Robotics. Year: 2018. Volume: 8 , Issue: 2 , Pages: 190-200 .

Authors: Saha A.;Pradhan S.N.

10.1504/IJCVR.2018.091980

LDO based noise minimization of active mode power gated circuit

Open Access

Article

Year: 2018. Volume: 31 , Issue: 4 , Pages: 188-195 .

Authors: Nath D.;Pradhan S.

10.5829/ije.2018.31.04a.01

Test power reduction by simultaneous do not care filling and ordering of test patterns considering pattern dependency

Open Access

Article

Year: 2018. Volume: 31 , Issue: 5 , Pages: 752-758 .

Authors: Sarkar T.;Pradhan S.

10.5829/ije.2018.31.05b.10

Area-power-temperature aware AND-XOR network synthesis based on Shared Mixed Polarity Reed-Muller expansion

Open Access

Article

Year: 2018. Volume: 10 , Issue: 12 , Pages: 35-46 .

Authors: Das A.;Pradhan S.

10.5815/ijisa.2018.12.04

Leakage Reduction of SRAM-Based Look-Up Table Using Dynamic Power Gating

Open Access

Article

Year: 2017. Volume: 26 , Issue: 3 .

Authors: Nag A.;Nath D.;Pradhan S.N.

10.1142/S0218126617500414

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