Ministry of Education
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Dr Pallabi Sarkar

vidwan id: 343883
Female

Assistant Professor, School of Electrical and Electronics Engineering
VIT Bhopal University, Sehore

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Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 18
Books 0
Proceedings 0

Publications

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Scopus

Citations 76
h-index 4

CrossRef

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Citations 59
h-index 4
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Professional Recognition

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Community & Membership

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Bio

Digital VLSI Design and Optimization, Digital Design with FPGA , Algorithm based design on CAD for VLSI and ASIC Designing, Design Space Exploration and High Level Synthesis.

Personal Details

  • Female
  • Assistant Professor , VIT Bhopal University, Sehore
  • VIT Bhopal University, Kothrikalan
PhD
Other Institute 2020
Assistant Professor Dec 2018 – Present
VIT Bhopal University, Sehore | School of Electrical and Electronics Engineering

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Co-Authors (3)

Anirban

Dr Anirban Sengupta

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Scholarly Work

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Scholarly Publications

Securing IP Cores in CE Systems using Key-driven Hash-chaining based Steganography

Open Access
Conference Paper
Year: 2020. Volume: 2020-November .
Authors: Rathor M.;Sarkar P.;Mishra V.K.;Sengupta A.
DOI 10.1109/ICCE-Berlin50680.2020.9352192
4 3

Performance Analysis of Radio Frequency (RF) Low Noise Amplifier (LNA) with various Transistor Configurations

Open Access
Conference Paper
Year: 2020. Pages: 88-91 .
Authors: Mayuresh Madhav Joshi ., Ribu Mathew ., Pallabi Sarkar ., Arya Dutt ., Sanjana Tiwari ., Prakhar Nigam .,
DOI 10.1109/ICDCS48716.2020.243555
6 4

Signature-free watermark for protecting digital signal processing cores used in CE devices [Hardware matters]

Open Access
Article
IEEE Consumer Electronics Magazine. Year: 2019. Volume: 8 , Issue: 1 , Pages: 92-94 .
Authors: Sarkar P.;Roy D.;Sengupta A.;Naskar M.
DOI 10.1109/MCE.2018.2867978
2 3

Obfuscation of fault secured DSP design through hybrid transformation

Open Access
Conference Paper
Year: 2018. Volume: 2018-July , Pages: 732-737 .
Authors: Sengupta A.;Neema S.;Sarkar P.;Harsha S.;Mohanty S.P.;Naskar M.K.
DOI 10.1109/ISVLSI.2018.00138
2 4

High Level Synthesis Methodology for Exploring Loop Unrolling Factor and Functional Datapath

Open Access
Conference Paper
Year: 2018.
Authors: Sarkar P.;Naskar M.K.;Sengupta A.
DOI 10.1109/ICACAT.2018.8933661

Optimizing DSP Cores Using Design Transformation [Hardware Matters]

Open Access
Article
IEEE Consumer Electronics Magazine. Year: 2018. Volume: 7 , Issue: 4 , Pages: 91-94 .
Authors: Roy D.;Sarkar P.;Sengupta A.;Naskar M.
DOI 10.1109/MCE.2018.2816207
1 1

Designing Low-Cost Hardware Accelerators for CE Devices [Hardware Matters]

Open Access
Article
IEEE Consumer Electronics Magazine. Year: 2017. Volume: 6 , Issue: 4 , Pages: 140-149 .
Authors: Sarkar P.;Sengupta A.;Rathlavat S.;Naskar M.
DOI 10.1109/MCE.2017.2714274
2 4

A firefly algorithm driven approach for high level synthesis

Open Access
Conference Paper
Year: 2017. Volume: 2018-February , Pages: 15-19 .
Authors: Sarkar P.;Sengupta A.;Rathlavat S.;Naskar M.K.
DOI 10.1109/iNIS.2017.13
2