Ministry of Education
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Dr Chandrashaker Pittala

vidwan id: 247814
Male

,

Orchid Icon 0000-0002-5968-7973 Google Scholar Icon 56260882200 Google Scholar Icon 8BuWTPEAAAAJ

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 21
Books 0
Proceedings 0

Publications

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Scopus

Citations 180
h-index 9

CrossRef

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Citations 73
h-index 6
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Professional Recognition

2021

Young Scientist

Vgood factory

Community & Membership

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Bio

Integrated Circuits, VLSI

Personal Details

  • Male
  • Dundigal, Telangana, India
Ph.D
Other Institute 2016
Associate Professor Dec 2016 – Sep 2022
MLR Institute of Technology

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Organisation (0)

no data

Co-Authors (15)

Ajitha

Ajitha G

Institute of Aeronautical Engineering

Avireni

Prof Avireni Srinivasulu

Mohan Babu University

Chaitanya

Mr Chaitanya Kancharapu

Vignan's Institute of Information Technology, Beside VSEZ, Duvvada, Gajuwaka,Vadlapudi (P.O)Pin-530049 (CC-L3)

Chaitanya

Mr Chaitanya Kancharapu

N/A

S. China

Dr S. China Venkateswarlu

N/A

SVS

Dr SVS Prasad

MLR Institute of Technology

M

M Lavanya

N/A

Mulkala

Mulkala Saritha

N/A

Sreevani

Sreevani Menda

Institute of Aeronautical Engineering

Karthik

Dr Karthik Rajendra

Reva University, Bangalore

Khadir

Mr Khadir Mohammad

Institute of Aeronautical Engineering

S.

Dr S. Kiran

Woxsen University

Jujavarapu

Jujavarapu Sravana

Malla Reddy Engineering College for women

Vijay

Dr Vijay V

N/A

Vijetha

Vijetha T

MLR Institute of Technology

Scholarly Work

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Scholarly Publications

Universal Shift Register Designed at Low Supply Voltages in 20 nm FinFET Using Multiplexer

Open Access
Conference Paper
Year: 2022. Volume: 213 , Pages: 203-212 .
Authors: Vallabhuni R.R.;Sravana J.;Pittala C.S.;Divya M.;Rani B.M.S.;Vijay V.
DOI 10.1007/978-981-16-2422-3_17
8

Universal Shift Register Designed at Low Supply Voltages in 15 nm CNTFET Using Multiplexer

Open Access
Conference Paper
Year: 2022. Volume: 292 , Pages: 597-605 .
Authors: Vallabhuni R.R.;Saritha M.;Chikkapally S.;Vijay V.;Pittala C.S.;Shaik S.
DOI 10.1007/978-981-16-4435-1_58

Design of 1-Bit FinFET Sum Circuit for Computational Applications

Open Access
Conference Paper
Year: 2022. Volume: 292 , Pages: 590-596 .
Authors: Pittala C.;Vijay V.
DOI 10.1007/978-981-16-4435-1_57
2

Numerical analysis of various plasmonic MIM/MDM slot waveguide structures

Open Access
Article
International Journal of System Assurance Engineering and Management. Year: 2022. Volume: 13 , Issue: 5 , Pages: 2551-2558 .
Authors: Pittala C.S.;Vallabhuni R.R.;Vijay V.;Anam U.R.;Chaitanya K.
DOI 10.1007/s13198-022-01664-8
5 3

Road identification through efficient edge segmentation based on morphological operations

Open Access
journal-article
Traitement du Signal. Year: 2021. Volume: 38 , Issue: 5 , Pages: 1503-1508 .
Authors: Rani, B.M.S.;Majety, V.D.;Pittala, C.S.;Vijay, V.;Sandeep, K.S.;Kiran, S.
DOI 10.18280/ts.380526
1

ECG performance validation using operational transconductance amplifier with bias current

Open Access
Article
International Journal of System Assurance Engineering and Management. Year: 2021. Volume: 12 , Issue: 6 , Pages: 1173-1179 .
Authors: Vijay V.;Reddy C.V.S.K.;Pittala C.S.;Vallabhuni R.R.;Saritha M.;Lavanya M.;Venkateswarlu S.C.;Sreevani M.
6

Novel Methodology to Validate DUTs Using Single Access Structure

Open Access
Conference Paper
Year: 2021.
Authors: Pittala C.S.;Sravana J.;Ajitha G.;Saritha P.;Khadir M.;Vijay V.;Venkateswarlu S.C.;Vallabhuni R.R.
DOI 10.1109/IEMENTech53263.2021.9614863
20

Biasing Techniques: Validation of 3 to 8 Decoder Modules Using 18nm FinFET Nodes

Open Access
conference-paper
Year: 2021.
Authors:
4 24