Dr Sanjay Vidhyadharan

vidwan id: 230819

Male

Assistant Professor, Department of WILP
Birla Institute of Technology and Science

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Expertise

Electrical and Electronic Engineering

Publications

Total Articles 34

Books 0

Proceedings 0

Publications

Scopus

Citations 154

h-index 8

CrossRef

Citations 193

h-index 8

Google Scholar

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Professional Recognition

2006

Chief of Air Staff Commendation

Indian Airforce

Community & Membership

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Bio

VLSI Design

Personal Details

Male
Assistant Professor , Birla Institute of Technology and Science
BITS Pilanai

PhD

Other Institute 2020

M.Tech

Other Institute 2010

B.E

Other Institute 1994

Assistant Professor Aug 2021 – Present

Birla Institute of Technology and Science | Department of WILP

Engineer Nov 1994 – Aug 2016

Indian Air Force

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Experts (19623+)

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Assistant Professor

Assistant Professor

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Assistant Professor

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Doctor

Assistant Professor (Grade-I)

Dr N PRAKASH

Assistant Professor

Mr Mrinmoy Sadhukhan

Research Scholar

Mr Haranath Rakshit

Junior Research Fellow

Organisations (1053+)

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Dr Brij Kishor Pandey

Assistant Professor

Dr VVSN Prabhakar Rao Budhiraju

Professor

Dr Brajesh Kumar Panigrahi

Assistant Professor

Dr Bahurudeen A

Associate Professor

Dr Balaji Krishnamurthy

Professor

Dr Arun Kumar Kulkarni

Professor

Prof Aruna Malapati

Professor

Dr Arun Kumar Jalan

Associate Professor

Dr ARUNKUMAR PALANIAPPAN

Associate Professor

Dr Atish Tulshiram Paul

Associate Professor

Co-Authors (3)

Dr Jitendra Kanungo

Jaypee University of Engeenering & Technology, Guna

Dr Ramakant

Mahindra University, Hyderabad

Dr Surya Shankar Dan

Birla Institute of Technology and Science

Scholarly Work

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Scholarly Publications

An advanced adiabatic logic using Gate Overlap Tunnel FET (GOTFET) devices for ultra-low power VLSI sensor applications

Open Access

Article

Analog Integrated Circuits and Signal Processing. Year: 2019. Volume: 102 , Issue: 1 , Pages: 111-123 .

Authors: Vidhyadharan S.;Yadav R.;Hariprasad S.;Dan S.

10.1007/s10470-019-01561-4

A nanoscale gate overlap tunnel FET (GOTFET) based improved double tail dynamic comparator for ultra-low-power VLSI applications

Open Access

Article

Analog Integrated Circuits and Signal Processing. Year: 2019. Volume: 101 , Issue: 1 , Pages: 109-117 .

Authors: Vidhyadharan S.;Yadav R.;Simhadri H.;Dan S.S.

10.1007/s10470-019-01487-x

Novel low and high threshold TFET based NTI and PTI cells benchmarked with standard 45 nm CMOS technology for ternary logic applications

Open Access

Conference Paper

Year: 2019. Pages: 419-424 .

Authors: Ramakant S.;Krishna Shyam A.;Hirpara M.;Chaudhary T.;Dan S.

10.1109/VLSID.2019.00090

Part i: Optimization of the tunnel fet device structure for achieving circuit performance better than the current standard 45 nm cmos technology

Open Access

Conference Paper

Year: 2019. Volume: 215 , Pages: 611-618 .

Authors: Ramakant ;Vidhyadharan S.;Akhilesh G.;Gupta V.;Ravi A.;Dan S.S.

10.1007/978-3-319-97604-4_95

Part ii: Benchmarking the performance of optimized tfet-based circuits with the standard 45 nm cmos technology using device & circuit co-simulation methodology

Open Access

Conference Paper

Year: 2019. Volume: 215 , Pages: 619-628 .

Authors: Vidhyadharan S.;Ramakant ;Akhilesh G.;Gupta V.;Ravi A.;Dan S.S.

10.1007/978-3-319-97604-4_96

Part II: Benchmarking the Performance of Optimized TFET-Based Circuits with the Standard 45 Nm CMOS Technology Using Device \& Circuit Co-Simulation Methodology

Open Access

inproceedings

Year: 2019. Pages: 619-628 .

Authors: Vidhyadharan, Sanjay and Yadav, Ramakant and Akhilesh, Gangishetty and Gupta, Vaibhav and Ravi, Anand and Dan, Surya Shankar

A Nanoscale Gate-Overlap Tunnel FET (GOTFET) Based Improved Double Tail Dynamic Comparator for Ultra-Low-Power VLSI Applications

Open Access

article

Year: 2019. Pages: 109-117 .

Authors: Sanjay Vidhyadharan ., Ramakant Yadav ., Hariprasad Simhadri ., Surya Shankar Dan .,

10.1007/s10470-019-01487-x

'Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC '

Open Access

article

Year: 0000. Volume: '73 ' , Pages: '101 - 113 ' .

Authors: 'Sanjay Vidhyadharan and Surya Shankar Dan and S.V. Abhay and Ramakant Yadav and Simhadri Hariprasad '

10.1016/j.vlsi.2020.03.006

Showing 25 to 32 of 34 results

Dr Sanjay Vidhyadharan

Expertise

Publications

Publications

Scopus

CrossRef

Google Scholar

Professional Recognition

Chief of Air Staff Commendation

Community & Membership

No Data Found

No Data Found

Bio

Personal Details

Related Profiles

Experts (19623+)

Organisations (1053+)

Co-Authors (3)

Scholarly Work

No Data Found

No Data Found

No Data Found

Scholarly Publications

An advanced adiabatic logic using Gate Overlap Tunnel FET (GOTFET) devices for ultra-low power VLSI sensor applications

A nanoscale gate overlap tunnel FET (GOTFET) based improved double tail dynamic comparator for ultra-low-power VLSI applications

Novel low and high threshold TFET based NTI and PTI cells benchmarked with standard 45 nm CMOS technology for ternary logic applications

Part i: Optimization of the tunnel fet device structure for achieving circuit performance better than the current standard 45 nm cmos technology

Part ii: Benchmarking the performance of optimized tfet-based circuits with the standard 45 nm cmos technology using device &amp; circuit co-simulation methodology

Part II: Benchmarking the Performance of Optimized TFET-Based Circuits with the Standard 45 Nm CMOS Technology Using Device \& Circuit Co-Simulation Methodology

A Nanoscale Gate-Overlap Tunnel FET (GOTFET) Based Improved Double Tail Dynamic Comparator for Ultra-Low-Power VLSI Applications

'Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC '

Part ii: Benchmarking the performance of optimized tfet-based circuits with the standard 45 nm cmos technology using device & circuit co-simulation methodology