Ministry of Education
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Dr Kariyappa B S B S

vidwan id: 209928
Male

Professor, Department of Electronics and Communication Engineering
R V College of Engineering, Bangalore

Orchid Icon 0000-0002-1118-3581 Google Scholar Icon 35102416500 Researcher Icon 0-6905-2016 Google Scholar Icon 0GphgFQAAAAJ

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 42
Books 0
Proceedings 0

Publications

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Scopus

Citations 386
h-index 7

CrossRef

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Citations 347
h-index 8
Google Scholar

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Professional Recognition

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Community & Membership

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Bio

VLSI Design

Personal Details

  • Male
  • Professor , R V College of Engineering, Bangalore
  • R V College of Engineering, R V Vidyanikethan Post, Mysuru Road
Ph.D
Other Institute 2012
Professor Dec 1999 – Present
R V College of Engineering, Bangalore | Department of Electronics and Communication Engineering

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Organisations (296+)

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B

Dr B Sathish Babu

Head of the Department

Badrinath

Dr Badrinath K

Associate Professor

Azra

Dr Azra Nasreen

Associate Professor

Arunkumar

Mr Arunkumar P Chavan

Assistant Professor

Avadhani

Dr Avadhani D N

Associate Professor

Ashok Kumar

Dr Ashok Kumar A R

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Dr Ashwani Sharma

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Dr Ashwini K B

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Prof Ashwin Thammaiah K

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Dr Basavaraja R J

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Co-Authors (9)

Kurian

Dr Kurian M Z

Sri Siddharatha Acedemy of Higher Education

Nagaraj

Prof Nagaraj Ramrao

Mohan Babu University

Pawankumar

Mr Pawankumar Bellary

R V College of Engineering, Bangalore

Praveen Kumar

Dr Praveen Kumar Gupta

R V College of Engineering, Bangalore

Praveen Kumar

Dr Praveen Kumar Y G

Sri Siddharatha Acedemy of Higher Education

Prema

Dr Prema V

BMS College of Engineering

Ravi

Dr Ravi Hosamani

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Shalini

Dr Shalini Shravan

N/A

Uma

Ms Uma Bv

R V College of Engineering, Bangalore

Scholarly Work

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Scholarly Publications

Performance analysis of integrated ADC DAC with PLL for future communication systems

Open Access
Conference Paper
Year: 2018. Pages: 1259-1263 .
Authors: Meti S.S.;Kariyappa B.S.
DOI 10.1109/RTEICT42901.2018.9012128

Fault Isolation in Analog Circuits using Multi-Support Vector Neural Network

Open Access
Conference Paper
Year: 2018. Pages: 655-660 .
Authors: Dennis B.;Kariyappa B.
DOI 10.1109/CESYS.2018.8723951
1

Implementation of power efficient 8-bit reversible linear feedback shift register for BIST

Open Access
Conference Paper
Year: 2017.
Authors: Kumar Y.G.P.;Kariyappa B.S.;Kurian M.Z.
DOI 10.1109/ICISC.2017.8068620
8 5

Design of common source amplifier using amorphous silicon TFT

Open Access
Conference Paper
Year: 2017. Volume: 394 , Pages: 229-236 .
Authors: Srikanth G.;Kariyappa B.;Uma B.
DOI 10.1007/978-981-10-1540-3_24

Design and optimization of 8 bit ALU using reversible logic

Open Access
Conference Paper
Year: 2017. Pages: 1632-1636 .
Authors: Deeptha A.;Muthanna D.;Dhrithi M.;Pratiksha M.;Kariyappa B.
DOI 10.1109/RTEICT.2016.7808109
9 6

Parametric analysis of amorphous silicon thin film transistors

Open Access
Conference Paper
Year: 2017. Pages: 1642-1646 .
Authors: Srikanth G.;Kariyappa B.;Uma B.
DOI 10.1109/RTEICT.2016.7808111

A survey on fault diagnosis of analog circuits: Taxonomy and state of the art

Open Access
Review
AEU - International Journal of Electronics and Communications. Year: 2017. Volume: 73 , Pages: 68-83 .
Authors: Binu D.;Kariyappa B.S.
DOI 10.1016/j.aeue.2017.01.002
64 68

Testing and validation of UART using cloud based GUI

Open Access
Conference Paper
Year: 2017. Volume: 2018-January , Pages: 782-786 .
Authors: Kiran B.M.;Madhusudhan C.;Farhan M.M.;Manzoor M.B.;Kariyappa B.S.
DOI 10.1109/RTEICT.2017.8256704
1 1