Ministry of Education
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Dr Kariyappa B S B S

vidwan id: 209928
Male

Professor, Department of Electronics and Communication Engineering
R V College of Engineering, Bangalore

Orchid Icon 0000-0002-1118-3581 Google Scholar Icon 35102416500 Researcher Icon 0-6905-2016 Google Scholar Icon 0GphgFQAAAAJ

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 42
Books 0
Proceedings 0

Publications

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Scopus

Citations 386
h-index 7

CrossRef

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Citations 347
h-index 8
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Professional Recognition

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Community & Membership

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Bio

VLSI Design

Personal Details

  • Male
  • Professor , R V College of Engineering, Bangalore
  • R V College of Engineering, R V Vidyanikethan Post, Mysuru Road
Ph.D
Other Institute 2012
Professor Dec 1999 – Present
R V College of Engineering, Bangalore | Department of Electronics and Communication Engineering

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Organisations (296+)

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B

Dr B Sathish Babu

Head of the Department

Badrinath

Dr Badrinath K

Associate Professor

Azra

Dr Azra Nasreen

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Arunkumar

Mr Arunkumar P Chavan

Assistant Professor

Avadhani

Dr Avadhani D N

Associate Professor

Ashok Kumar

Dr Ashok Kumar A R

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Dr Ashwani Sharma

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Ashwini

Dr Ashwini K B

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Ashwin

Prof Ashwin Thammaiah K

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Basavaraja

Dr Basavaraja R J

Associate Professor

Co-Authors (9)

Kurian

Dr Kurian M Z

Sri Siddharatha Acedemy of Higher Education

Nagaraj

Prof Nagaraj Ramrao

Mohan Babu University

Pawankumar

Mr Pawankumar Bellary

R V College of Engineering, Bangalore

Praveen Kumar

Dr Praveen Kumar Gupta

R V College of Engineering, Bangalore

Praveen Kumar

Dr Praveen Kumar Y G

Sri Siddharatha Acedemy of Higher Education

Prema

Dr Prema V

BMS College of Engineering

Ravi

Dr Ravi Hosamani

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Shalini

Dr Shalini Shravan

N/A

Uma

Ms Uma Bv

R V College of Engineering, Bangalore

Scholarly Work

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Scholarly Publications

RideNN: A New Rider Optimization Algorithm-Based Neural Network for Fault Diagnosis in Analog Circuits

Open Access
Article
IEEE Transactions on Instrumentation and Measurement. Year: 2019. Volume: 68 , Issue: 1 , Pages: 2-26 .
Authors: Binu D.;Kariyappa B.S.
DOI 10.1109/TIM.2018.2836058
153 158

Design and Simulation of High-Performance 2D Convolution Architecture

Open Access
Conference Paper
Year: 2018. Volume: 471 , Pages: 371-380 .
Authors: Vishal V.;Kariyappa B.
DOI 10.1007/978-981-10-7329-8_38

Support Vector Neural Network and Principal Component Analysis for Fault Diagnosis of Analog Circuits

Open Access
Conference Paper
Year: 2018. Pages: 1152-1157 .
Authors: Binu D.;Karivappa B.S.
DOI 10.1109/ICOEI.2018.8553786
2 3

SRAM design using memristor and self-controllable voltage (SVL) technique

Open Access
Book Chapter
Year: 2018. Volume: 9 , Pages: 29-39 .
Authors: Kumar N.S.;Sudhanva N.G.;Hande V.S.;Sajjan M.V.;Kumar C.S.H.;Kariyappa B.S.
DOI 10.1007/978-981-10-6319-0_3
3 2

Analysis of low power 7T SRAM cell employing improved SVL (ISVL) technique

Open Access
Conference Paper
Year: 2018. Volume: 2018-January , Pages: 478-482 .
Authors: Kumar C.S.H.;Kariyappa B.S.
DOI 10.1109/ICEECCOT.2017.8284551
4 5

Design and comparitive analysis of memristor and magnetic tunnel junction (MTJ) based non-volatile SRAM cell

Open Access
Conference Paper
Year: 2018. Pages: 1097-1102 .
Authors: Shilpa R.;Achar P.E.;Roja M.;Sindu G.R.;Kariyappa B.
DOI 10.1109/RTEICT42901.2018.9012346

Static low-power 17T true single phase clocking flip-flop based on logic structure optimization

Open Access
Conference Paper
Year: 2018. Pages: 680-685 .
Authors: Ajay Kumar G.C.;Bagewadi S.N.;Kariyappa B.S.
DOI 10.1109/RTEICT42901.2018.9012588

Design and power analysis of 16×16 SRAM Array Employing 7T I-LSVL

Open Access
Conference Paper
Year: 2018. Pages: 319-322 .
Authors: Hemanth Kumar C.S.;Kariyappa B.S.
DOI 10.1109/RTEICT42901.2018.9012414
3