Ministry of Education
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Mr Kamalaksha Baral

vidwan id: 207506
Male

Assistant Professor, Department of Electronics and Communication Engineering
Padmasri Dr. B.V Raju Institute of Technology

Orchid Icon 0000-0001-8546-8021 Google Scholar Icon 57193269013 Google Scholar Icon zv6zxUcAAAAJ

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 51
Books 0
Proceedings 0

Publications

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Scopus

Citations 948
h-index 16

CrossRef

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Citations 747
h-index 13
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Professional Recognition

2014

UGC NET

UGC
2012

GATE

IIT
2013

GATE

IIT
2016

GATE

IIT

Community & Membership

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Bio

Kamalaksha Baral, PhD(IIT-BHU), Assistant Professor, BVRIT

Personal Details

  • Male
  • Assistant Professor , Padmasri Dr. B.V Raju Institute of Technology
  • Narsapur, Telangana, India
PhD
Other Institute 2021
Assistant Professor Apr 2021 – Present
Padmasri Dr. B.V Raju Institute of Technology | Department of Electronics and Communication Engineering

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Co-Authors (16)

Amit

Dr Amit Kumar

National Institute of Technology Jamshedpur

Ashish Kumar

Dr Ashish Kumar Singh

Graphic Era University, Dehradun

Bratindranath

Dr Bratindranath Mukherjee

Indian Institute of Technology (BHU), Varanasi

Chandan

Dr Chandan Kumar

SUPAUL COLLEGE OF ENGINEERING

Ekta

Dr Ekta Goel

National Institute of Technology Warangal

Gopal

Dr Gopal Rawat

N/A

Hemant

Dr Hemant Kumar

Jaypee Institute of Information Technology, Noida

Kunal

Dr Kunal Singh

National Institute of Technology Jamshedpur

Manas Ranjan

Prof Manas Ranjan Tripathy

National Institute of Technology Rourkela

Rishibrind Kumar

Dr Rishibrind Kumar Upadhyay

Jaypee Institute of Information Technology, Noida

Rishbrind Kumar

Dr Rishbrind Kumar Upadhyay

S R M Institute of Science & Technology, Chennai

Sanjay

Prof Sanjay Kumar

Indian Institute of Technology Madras

Srimanta

Prof Srimanta Baishya

National Institute of Technology Silchar

Satyabrata

Prof Satyabrata Jit

Indian Institute of Technology (BHU), Varanasi

Vinodhkumar

Dr Vinodhkumar N

Vel Tech Rangarajan Dr. Sagunthala R & D Institute of Science & Technology, Chennai

Kunal

Dr Kunal Singh

National Institute of Technology Jamshedpur

Scholarly Work

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Scholarly Publications

Two-dimensional analytical modeling for electrical characteristics of Ge/Si SOI-tunnel FinFETs

Open Access
Article
Superlattices and Microstructures. Year: 2019. Volume: 131 , Pages: 30-39 .
Authors: Chander S.;Baishya S.;Sinha S.K.;Kumar S.;Singh P.K.;Baral K.;Tripathy M.R.;Singh A.K.;Jit S.
DOI 10.1016/j.spmi.2019.05.037
33 37

Dual Material-Stacked Hetero-Dielectric-Junctionless Accumulation Mode Nanotube MOSFET for enhanced Hot Carrier and Trapped Charges Reliability

Open Access
Conference Paper
Year: 2019. Pages: 330-332 .
Authors: Baral K.;Singh P.K.;Kumar S.;Chander S.;Tripathy M.R.;Jit S.
DOI 10.1109/EDTM.2019.8731216
2 2

Ultrathin Body Nanowire Hetero-dielectric Stacked Asymmetric Halo Doped Junction less Accumulation Mode MOSFET for Enhanced Electrical Characteristics and Negative Bias Stability

Open Access
article
Year: 2019.
Authors: Kamalaksha Baral
DOI 10.1016/j.spmi.2019.106364

New Topologies of a Lossless Grounded Negative Inductor Using Single CDBA

Open Access
Conference Paper
Year: 2019.
Authors: Jarwal D.K.;Baral K.;Singh A.K.;Singh P.K.;Jit S.
DOI 10.1109/IEMENTech48150.2019.8981374
1 1

Impact of Gate Dielectrics on Analog/RF Performance of Double Gate Tunnel Field Effect Transistor

Open Access
Conference Paper
Year: 2019.
Authors: Singh P.K.;Baral K.;Chander S.;Kumar S.;Tripathy M.R.;Singh A.K.;Jit S.
DOI 10.1109/IEMENTech48150.2019.8981283
3 4

Performance investigation of a p-channel hetero-junction GaN Tunnel FET

Open Access
Conference Paper
Year: 2019.
Authors: Tripathy M.R.;Kumar Singh A.;Samad A.;Chander S.;Singh P.K.;Baral K.;Jarwal D.K.;Kumar Mishra A.;Jit S.
DOI 10.1109/IMaRC45935.2019.9118671
1 4

Study and Investigation of DC and RF Performance of TFET on SEL-BOX and Conventional SOI TFET with SiO2/HfO2 Stacked Gate Structure

Open Access
Conference Paper
Year: 2019.
Authors: Singh A.K.;Barah D.;Tripathy M.R.;Baral K.;Chander S.;Singh P.K.;Jit S.
DOI 10.1109/IEMENTech48150.2019.8981284
2 3

2-D analytical drain current model of double-gate heterojunction TFETs with a SiO2/HfO2 stacked gate-oxide structure

Open Access
Article
IEEE Transactions on Electron Devices. Year: 2018. Volume: 65 , Issue: 1 , Pages: 331-338 .
Authors: Kumar S.;Singh K.;Chander S.;Goel E.;Singh P.K.;Baral K.;Singh B.;Jit S.
DOI 10.1109/TED.2017.2773560
66 68