Mr Kamalaksha Baral

vidwan id: 207506

Male

Assistant Professor, Department of Electronics and Communication Engineering
Padmasri Dr. B.V Raju Institute of Technology

0000-0001-8546-8021 Google Scholar Icon

57193269013 Google Scholar Icon

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Expertise

Electrical and Electronic Engineering

Publications

Total Articles 51

Books 0

Proceedings 0

Publications

Scopus

Citations 948

h-index 16

CrossRef

Citations 747

h-index 13

Google Scholar

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Professional Recognition

2014

UGC NET

UGC

2012

GATE

IIT

2013

GATE

IIT

2016

GATE

IIT

Community & Membership

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Bio

Kamalaksha Baral, PhD(IIT-BHU), Assistant Professor, BVRIT

Personal Details

Male
Assistant Professor , Padmasri Dr. B.V Raju Institute of Technology
Narsapur, Telangana, India

PhD

Other Institute 2021

Assistant Professor Apr 2021 – Present

Padmasri Dr. B.V Raju Institute of Technology | Department of Electronics and Communication Engineering

Related Profiles

Experts (19623+)

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Assistant Professor

Assistant Professor

N/A

Assistant Professor

Assistant Professor

Doctor

Assistant Professor (Grade-I)

Dr N PRAKASH

Assistant Professor

Mr Mrinmoy Sadhukhan

Research Scholar

Mr Haranath Rakshit

Junior Research Fellow

Organisations (395+)

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Assistant Professor

Assistant Professor

Associate Professor

Assistant Professor

Assistant Professor

Professor

Dr Ashok Kumar Kusuma

Assistant Professor

Dr Ashok Kumar Nanda

Associate Professor

Mr Ashok Kumar.R

Assistant Professor

Asharani Pattedar

Assistant Professor

Co-Authors (16)

Dr Amit Kumar

National Institute of Technology Jamshedpur

Dr Ashish Kumar Singh

Graphic Era University, Dehradun

Dr Bratindranath Mukherjee

Indian Institute of Technology (BHU), Varanasi

Dr Chandan Kumar

SUPAUL COLLEGE OF ENGINEERING

Dr Ekta Goel

National Institute of Technology Warangal

Dr Gopal Rawat

N/A

Dr Hemant Kumar

Jaypee Institute of Information Technology, Noida

Dr Kunal Singh

National Institute of Technology Jamshedpur

Prof Manas Ranjan Tripathy

National Institute of Technology Rourkela

Dr Rishibrind Kumar Upadhyay

Jaypee Institute of Information Technology, Noida

Dr Rishbrind Kumar Upadhyay

S R M Institute of Science & Technology, Chennai

Prof Sanjay Kumar

Indian Institute of Technology Madras

Prof Srimanta Baishya

National Institute of Technology Silchar

Prof Satyabrata Jit

Indian Institute of Technology (BHU), Varanasi

Dr Vinodhkumar N

Vel Tech Rangarajan Dr. Sagunthala R & D Institute of Science & Technology, Chennai

Dr Kunal Singh

National Institute of Technology Jamshedpur

Scholarly Work

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Scholarly Publications

Impact of interface trap charges on electrical performance characteristics of a source pocket engineered Ge/Si heterojunction vertical TFET with HfO2/Al2O3 laterally stacked gate oxide

Open Access

Article

Microelectronics Reliability. Year: 2021. Volume: 119 .

Authors: Tripathy M.R.;Samad A.;Singh A.K.;Singh P.K.;Baral K.;Mishra A.K.;Jit S.

10.1016/j.microrel.2021.114073

Simple optical sensors for oxygen detection: simulation fabrication and characterization

Open Access

Article

Journal of Modern Optics. Year: 2021. Volume: 68 , Issue: 16 , Pages: 886-894 .

Authors: Satish Addanki ., Kamalaksha Baral ., N. Vinodh Kumar .,

10.1080/09500340.2021.1958946

Impact of ion implantation on stacked oxide cylindrical gate junctionless accumulation mode MOSFET: An electrical and circuit level analysis

Open Access

Article

Materials Science in Semiconductor Processing. Year: 2021. Volume: 133 .

Authors: Baral K.;Singh P.K.;Kumar G.;Singh A.K.;Tripathy M.R.;Kumar S.;Jit S.

10.1016/j.mssp.2021.105966

A 2-D compact DC model for engineered nanowire JAM-MOSFETs valid for all operating regimes

Open Access

Article

Year: 2020. Volume: 35 , Issue: 8 .

Authors: Baral K.;Singh P.K.;Kumar S.;Tripathy M.R.;Singh A.K.;Chander S.;Jit S.

10.1088/1361-6641/ab8fc0

Impact of Temperature on DC and AC Characteristics of Stacked Oxide SiO2/HfO2Cylindrical Gate Tunnel FETs

Open Access

Conference Paper

Year: 2020.

Authors: Singh P.K.;Baral K.;Kumar S.;Tripathy M.R.;Singh A.K.;Upadhyay R.K.;Jit S.

10.1109/ICEE50728.2020.9776990

Study of Temperature Sensitivity on Linearity Figures of Merit of Ge/Si Hetero-Junction Gate-Drain Underlapped Vertical Tunnel FET with heterogeneous gate dielectric structure for Improving Device Reliability

Open Access

Conference Paper

Year: 2020.

Authors: Tripathy M.R.;Kumar Singh A.;Baral K.;Singh P.K.;Kumar Mishra A.;Jarwal D.K.;Jit S.

10.23919/URSIRCRS49211.2020.9113520

Impact of interface trap charges on device level performances of a lateral/vertical gate stacked Ge/Si TFET-on-SELBOX-substrate

Open Access

Article

Year: 2020. Volume: 126 , Issue: 9 .

Authors: Singh A.K.;Tripathy M.R.;Baral K.;Singh P.K.;Jit S.

10.1007/s00339-020-03869-9

Investigation of DC, RF and linearity performances of a back-gated (BG) heterojunction (HJ) TFET-on-selbox-substrate (STFET): Introduction to a BG-HJ-STEFT based CMOS inverter

Open Access

Article

Microelectronics Journal. Year: 2020. Volume: 102 .

Authors: Singh A.K.;Tripathy M.R.;Baral K.;Singh P.K.;Jit S.

10.1016/j.mejo.2020.104775

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