Ministry of Education
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Dr Satheesh Kumar S

vidwan id: 190688
Male

Assistant Professor, School of Electronics Engineering
Vellore Institute of Technology, Vellore

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Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 11
Books 0
Proceedings 0

Publications

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Scopus

Citations 4
h-index 2

CrossRef

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Citations 1
h-index 1
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Professional Recognition

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Community & Membership

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Bio

Soft Errors, Low Power Circuit Design, Radiation Hardened Circuit Design

Personal Details

  • Male
  • Assistant Professor , Vellore Institute of Technology, Vellore
  • Vellore Institute of Technology
PhD
Other Institute 2019
Assistant Professor Aug 2009 – Present
Vellore Institute of Technology, Vellore | School of Electronics Engineering

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Co-Authors (6)

Jagannadha Naidu

Dr Jagannadha Naidu K

Vellore Institute of Technology, Vellore

Kumaravel

Dr Kumaravel S

Vellore Institute of Technology, Vellore

Pulidindi

Dr Pulidindi Venugopal

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Rajeev

Mr Rajeev Nelapati

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Dr Srinivas Koppu

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Dr Venugopal P

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Scholarly Work

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Scholarly Publications

A low power and soft error resilience guard-gated Quartro-based flip-flop in 45 nm CMOS technology

Open Access
Article
Year: 2021. Volume: 15 , Issue: 6 , Pages: 571-580 .
Authors: Sabavat Satheesh Kumar ., Kumaravel Sundaram ., Sanjeevikumar Padmanaban ., Jens Bo Holm‐Nielsen ., Frede Blaabjerg .,
DOI 10.1049/cds2.12052

Design and analysis of SEU hardened latch for low power and high speed applications

Open Access
Article
Journal of Low Power Electronics and Applications. Year: 2019. Volume: 9 , Issue: 3 .
Authors: Satheesh Kumar S.;Kumaravel S.
DOI 10.3390/jlpea9030021
1 2

Low power and high reliable Triple Modular Redundancy latch for single and multi-node upset mitigation

Open Access
Article
International Journal of Advanced Computer Science and Applications. Year: 2019. Volume: 10 , Issue: 7 , Pages: 433-443 .
Authors: Satheesh Kumar S.;Kumaravel S.

Adaptive cruise control and cooperative cruise control in real life traffic situation

Open Access
Article
Year: 2018. Volume: 9 , Issue: 13 , Pages: 578-585 .
Authors: Ravikumar C.V.;Venugopal P.;Jagannadha Naidu K.;Satheesh Kumar S.;Koppu S.
2

A SEU Hardened Dual Dynamic Node Pulsed Hybrid Flip-Flop with an Embedded Logic Module

Open Access
Conference Paper
Year: 2018. Volume: 837 , Pages: 62-68 .
Authors: Adapur R.;Satheesh Kumar S.
DOI 10.1007/978-981-13-1936-5_7

SEU hardened DFF and 4 bit johnson counter using quatro latch in 45 nm technology

Open Access
Conference Paper
Year: 2017. Volume: 2017-January , Pages: 1-6 .
Authors: Katkar P.;Kumar S.S.;Kumaravel S.
DOI 10.1109/ICMDCS.2017.8211721

Design and analysis of 8T SRAM with assist schemes (UDVS) in 45nm CMOS

Open Access
Conference Paper
Year: 2017.
Authors: Chokkakula G.;Reddy N.S.;Devendra B.;Kumar S.S.
DOI 10.1109/ICCPCT.2017.8074346

Verification of master-slave using AMBA AXI-OCP protocol

Open Access
Article
Year: 2016. Volume: 8 , Issue: 3 , Pages: 17634-17644 .
Authors: Satheesh Kumar S.;Venugopal P.;Nelapati R.P.