Dr Narendar V

vidwan id: 154172

Male

Assistant Professor, Department of Electronics and Communication Engineering
National Institute of Technology Warangal

56342552600

Expertise

Electrical and Electronic Engineering

Publications

Total Articles 58

Books 0

Proceedings 0

Publications

Scopus

Citations 1062

h-index 21

CrossRef

Citations 838

h-index 18

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Bio

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Personal Details

Male
Assistant Professor , National Institute of Technology Warangal

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Assistant Professor Apr 2018 – Present

National Institute of Technology Warangal | Department of Electronics and Communication Engineering

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Dr N PRAKASH

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Mr Mrinmoy Sadhukhan

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Organisations (290+)

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Dr B Raghuram Kadali

Assistant Professor

Dr Srinivasa Rao B

Associate Professor

Dr Balaprakasa Rao Killi

Assistant Professor

Dr Arif Ali Baig Moghal

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Co-Authors (15)

Dr Hitesh Borkar

National Institute of Technology Warangal

Dr B. Naresh Kumar Reddy

National Institute of Technology Tiruchirappalli

Dr Vijay Lamba

Gurugram University, Gurugram

Dr Neeraj Kumar Misra

Vellore Institute of Technology (VIT-AP) University, Andhra Pradesh

Dr Pothalaiah S

Vignana Bharathi Institute of Technology

Dr R.A. Mishra

Motilal Nehru National Institute of Technology Allahabad

Dr Sankit Kassa

Symbiosis Institute of Technology

Shree Sarangam K

National Institute of Technology Warangal

Dr Satish Maheshwaram

National Institute of Technology Warangal

Dr Shweta Tripathi

Motilal Nehru National Institute of Technology Allahabad

Dr Santosh Kumar Gupta

Motilal Nehru National Institute of Technology Allahabad

Dr Santosh Kumar Padhi

University of Hyderabad

Dr Santosh Kumar Vishvakarma

Indian Institute of Technology Indore

Dr Vakkalakula Bharath Sreenivasulu

Reva University, Bangalore

Dr Vijay Lamba

Symbiosis Institute of Technology

Scholarly Work

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Scholarly Publications

Role of Dielectric-Semiconductor Interface Traps in Multilayer MoS2 FinFETs: An Investigation from Device to Circuit

Open Access

Article

IEEE Transactions on Dielectrics and Electrical Insulation. Year: 2025.

Authors: Kotha V.R.;Valasa S.;Vadthiya N.

10.1109/TDEI.2025.3570968

Design Space Optimization for Eradication of NDR Effect in Dielectric/Ferroelectric-Stacked Negative Capacitance Multigate FETs at Sub-3 nm Technology for Digital/ Analog/RF Applications

Open Access

Article

IEEE Transactions on Dielectrics and Electrical Insulation. Year: 2025. Volume: 32 , Issue: 2 , Pages: 769-778 .

Authors: Valasa S.;Ramakrishna Kotha V.;Tayal S.;Vadthiya N.

10.1109/TDEI.2024.3432088

Design and Optimization of Ferroelectric Spacer Engineered Modified Bi-Level Negative Capacitance FET: An Analog/RF Evaluation Perspective

Open Access

Article

IEEE Transactions on Dielectrics and Electrical Insulation. Year: 2025. Volume: 32 , Issue: 1 , Pages: 222-230 .

Authors: Padhi S.K.;Narendar V.;Nishad A.K.

10.1109/TDEI.2024.3449797

Interface Trap Characterization in Junctionless Forksheet FET at Sub-3 nm Technology Node: A Reliability Assessment on Digital, Analog/RF, and Circuit Applications

Open Access

Article

IEEE Transactions on Device and Materials Reliability. Year: 2025. Volume: 25 , Issue: 1 , Pages: 119-127 .

Authors: Ryali G.;Pitchuka B.S.;Kotha V.R.;Valasa S.;Bhukya S.;Mudidhe P.K.;Tayal S.;Vadthya B.;Borkar H.;Vadthiya N.

10.1109/TDMR.2024.3516084

Spacer Design Strategies at Sub-5-nm Technology Node for Junctionless Forksheet FET: Bridging Device Optimization and Circuit Efficacy - A Dielectric Perspective

Open Access

Article

IEEE Transactions on Dielectrics and Electrical Insulation. Year: 2025. Volume: 32 , Issue: 4 , Pages: 1997-2004 .

Authors: Gurre D.;Dasari V.;Mulaga K.;Valasa S.;Ramakrishna Kotha V.;Bhukya S.;Kumar Mudidhe P.;Tayal S.;Vadthya B.;Vadthiya N.

10.1109/TDEI.2024.3497877

Interface trap dynamics and thermal effects in novel junctionless dual gate inverted-U-shaped FinFETs for sub-5 nm node: device to circuit level implementation

Open Access

Article

Year: 2025. Volume: 58 , Issue: 13 .

Authors: Bandi B.P.;Sornapudi U.S.S.;Valasa S.;Kotha V.R.;Bhukya S.;Mudidhe P.K.;Tayal S.;Vadthiya N.

10.1088/1361-6463/adb046

Design Insights of Multilayer MoS2Fin-Shaped FETs for Digital and Analog/RF Applications

Open Access

Article

ACS Applied Electronic Materials. Year: 2025. Volume: 7 , Issue: 15 , Pages: 6747-6760 .

Authors: Kotha V.R.;Valasa S.;Vadthiya N.

10.1021/acsaelm.5c00204

Radiation Hardness on Dielectric/Ferroelectric Stacked Negative Capacitance Multi-Gate Metal Oxide Semiconductor FETs at Sub-3nm Technology Node: Device to CMOS Inverter Layout

Open Access

Article

IEEE Transactions on Dielectrics and Electrical Insulation. Year: 2025.

Authors: Valasa S.;Kotha V.R.;Vadthiya N.

10.1109/TDEI.2025.3582236

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