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Dr Ashwani Rana

vidwan id: 101432
Male

Associate Professor, Department of Electronics and Communication Engineering
National Institute of Technology, Hamirpur

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 73
Books 0
Proceedings 0

Publications

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Scopus

Citations 462
h-index 13

CrossRef

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Citations 269
h-index 10
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Bio

Modeling of Semiconductor Devices, Low Power High Performance VLSI Circuit Design and Emerging Integrated Circuit Technologies

Personal Details

  • Male
  • Associate Professor , National Institute of Technology, Hamirpur
  • Department of Electronics and Communication Engineering, National Institute of Technology, Hamirpur
Ph.D
National Institute of Technology, Hamirpur 2011
Associate Professor Aug 2000 – Present
National Institute of Technology, Hamirpur | Department of Electronics and Communication Engineering

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Co-Authors (11)

Amita

Dr Amita Nandal

Manipal University, Jaipur

Arvind

Dr Arvind Dhaka

Manipal University, Jaipur

Gaurav

Dr Gaurav Saini

National Institute of Technology Kurukshetra

GAURAV

Dr GAURAV SAINI

National Institute of Technology Kurukshetra

Pankaj Kumar

Dr Pankaj Kumar Pal

National Institute of Technology, Uttarakhand

Rajneesh

Dr Rajneesh Sharma

Thapar Institute of Engineering & Technology

Ashish

Dr Ashish Raman

Dr B R Ambedkar National Institute of Technology, Jalandhar

Rajeevan

Prof Rajeevan Chandel

National Institute of Technology, Hamirpur

Shalu

Dr Shalu K

University Institute of Information and Technology, H.P.U, Shimla

Sunil

Dr Sunil Jadav

J.C. Bose University of Science and Technology

Scholarly Work

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Scholarly Publications

Impact of high-k spacer on device performance of nanoscale underlap fully depleted soi mosfet

Open Access
Article
Authors: Sharma R.;Rathore R.;Rana A.

Design and structural optimization of junctionless FinFET with Gaussian-doped channel

Open Access
Article

Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET

Open Access
Article

Investigation of metal-gate work-function variability in FinFET structures and implications for SRAM cell design

Open Access
Article

Performance estimation of junctionless FinFET with graded channel design

Open Access
Conference Paper

Threshold voltage variability induced by statistical parameters fluctuations in nanoscale bulk and SOI FinFETs

Open Access
Conference Paper

Nanoscale static random-access-memory design using strained underlap ultra thin silicon on insulator mosfet for improved performance

Open Access
Article

Line edge roughness induced threshold voltage variability in nano-scale FinFETs

Open Access
Article