Prof Manas Ranjan Tripathy

vidwan id: 94640

Male

Assistant Professor, Department of Mathematics
National Institute of Technology Rourkela

38962197800

Expertise

Mathematics

Publications

Total Articles 45

Books 0

Proceedings 0

Publications

Scopus

Citations 665

h-index 15

CrossRef

Citations 438

h-index 11

Google Scholar

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Professional Recognition

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Community & Membership

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Bio

Statistics, Optimization and Discrete Mathematics, Statistical Inference, Computational Statistics

Personal Details

Male
Assistant Professor , National Institute of Technology Rourkela
Department of Mathematics, National Institute of Technology, Rourkela

PhD

Indian Institute of Technology Kharagpur 2009

Assistant Professor Jul 2011 – Present

National Institute of Technology Rourkela | Department of Mathematics

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Co-Authors (15)

Dr Adarsha Kumar Jena

National Institute of Technology, Meghalaya

Dr Amit Kumar

National Institute of Technology Jamshedpur

Dr Ashish Kumar Singh

Graphic Era University, Dehradun

Dr Bratindranath Mukherjee

Indian Institute of Technology (BHU), Varanasi

Dr Brinda Bhowmick

National Institute of Technology Silchar

Mr Kamalaksha Baral

Padmasri Dr. B.V Raju Institute of Technology

Dr Maheswar Rajagopal

KPR Institute of Engineering and Technology

Dr Rishibrind Kumar Upadhyay

Jaypee Institute of Information Technology, Noida

Dr Rishbrind Kumar Upadhyay

S R M Institute of Science & Technology, Chennai

Prof Sanjay Kumar

Indian Institute of Technology Madras

Prof Srimanta Baishya

National Institute of Technology Silchar

Prof Satyabrata Jit

Indian Institute of Technology (BHU), Varanasi

Dr Somesh Kumar

Indian Institute of Technology Kharagpur

Prof Ayas Kanta Swain

National Institute of Technology Rourkela

Prof Bhishma Tyagi

National Institute of Technology Rourkela

Scholarly Work

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Scholarly Publications

Design and Performance Assessment of HfO2/SiO2 Gate Stacked Ge/Si Heterojunction TFET on SELBOX Substrate (GSHJ-STFET)

Open Access

Article

Year: 2022. Volume: 14 , Issue: 17 , Pages: 11847-11858 .

Authors: Singh A.K.;Tripathy M.R.;Baral K.;Jit S.

10.1007/s12633-022-01898-y

Design and Simulation of Triple Material Gate InAs/Si Heterojunction TFET on SEL-BOX Substrates: Temperature Impact Analysis

Open Access

Conference Paper

Year: 2021.

Authors: Singh A.K.;Tripathy M.R.;Upadhyay R.K.;Jit S.

10.1109/GUCON50781.2021.9573526

Deep Insight into DC/RF and Linearity Parameters of a Novel Back Gated Ferroelectric TFET on SELBOX Substrate for Ultra Low Power Applications

Open Access

Article

Year: 2021. Volume: 13 , Issue: 11 , Pages: 3853-3863 .

Authors: Singh A.K.;Tripathy M.R.;Singh P.K.;Baral K.;Chander S.;Jit S.

10.1007/s12633-020-00672-2

Impact of interface trap charges on electrical performance characteristics of a source pocket engineered Ge/Si heterojunction vertical TFET with HfO2/Al2O3 laterally stacked gate oxide

Open Access

Article

Microelectronics Reliability. Year: 2021. Volume: 119 .

Authors: Tripathy M.R.;Samad A.;Singh A.K.;Singh P.K.;Baral K.;Mishra A.K.;Jit S.

10.1016/j.microrel.2021.114073

PM2.5 estimation using multiple linear regression approach over industrial and non-industrial stations of India

Open Access

Article

Journal of Ambient Intelligence and Humanized Computing. Year: 2021. Volume: 12 , Issue: 2 , Pages: 2975-2991 .

Authors: Gogikar P.;Tripathy M.R.;Rajagopal M.;Paul K.K.;Tyagi B.

10.1007/s12652-020-02457-2

Analytical Drain Current Model for Source Pocket Engineered Stacked Oxide SiO2/HfO2 Cylindrical Gate TFETs

Open Access

Article

Year: 2021. Volume: 13 , Issue: 6 , Pages: 1731-1739 .

Authors: Singh P.K.;Baral K.;Kumar S.;Tripathy M.R.;Singh A.K.;Upadhyay R.K.;Chander S.;Jit S.

10.1007/s12633-020-00563-6

Impact of ion implantation on stacked oxide cylindrical gate junctionless accumulation mode MOSFET: An electrical and circuit level analysis

Open Access

Article

Materials Science in Semiconductor Processing. Year: 2021. Volume: 133 .

Authors: Baral K.;Singh P.K.;Kumar G.;Singh A.K.;Tripathy M.R.;Kumar S.;Jit S.

10.1016/j.mssp.2021.105966

Lateral and Vertical Gate Oxide Stacking Impact on Noise Margins and Delays for the 8T SRAM Designed with Source Pocket Engineered GaSb/Si Heterojunction Vertical TFET: A Reliability Study

Open Access

Article

IEEE Transactions on Device and Materials Reliability. Year: 2021. Volume: 21 , Issue: 3 , Pages: 372-378 .

Authors: Tripathy M.R.;Jit S.

10.1109/TDMR.2021.3098437

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