Ministry of Education
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Dr Surajeet Ghosh

vidwan id: 94263
Male

Associate Professor, Department of Computer Science and Technology
Indian Institute of Engineering Science & Technology, Shibpur (formerly Bengal Engineering & Science University)

Orchid Icon 0000-0003-1428-9530 Google Scholar Icon 10440122200 Researcher Icon GPK-1821-2022 Google Scholar Icon M0CWcEYAAAAJ

Expertise

  • Computer Science Hardware and Architecture

Publications

Total Articles 36
Books 0
Proceedings 0

Publications

No publication activity to display at the moment.

Scopus

Citations 92
h-index 6

CrossRef

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Citations 25
h-index 3
Google Scholar

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Professional Recognition

2008

Gowri Memorial Award (GMA)

The Institution of Electronics and Telecommunication Engineers (IETE)
2009

Best Paper Award

International Conference on Advanced Computing (ICAC 09)
2013

Best Paper Award

IEEE International Conference on Computational Intelligence and Computing Research (IEEE ICCIC)

Community & Membership

2013

WBUT Winter School (Under TEQIP Programme), Kolkata

Organising Committee Member
2017

IEEE TENSYMP 2017

Technical Program Committee Member
2018

Fifth International Conference on Emerging Applications of Information Technology (EAIT)

International Program Committee
2018

IEEE International Conference on Computing Methodologies and Communication (ICCMC 2018)

Advisory Committee Member

Fourth International Symposium on Signal Processing and Intelligent Recognition Systems (S

Technical Program Committee Member
2018

IEEE Conference on Applied Signal Processing (ASPCON 2018)

Technical Program Committee Member

Fifth International Symposium on Signal Processing and Intelligent Recognition Systems (SI

Technical Program Committee Member
2016

IEEE Region 10 Conference (TENCON), Singapore

Reviewer
2017

IEEE TENSYMP 2017, Cochin, Kerala

Reviewer
2018

Fifth International Conference on Emerging Applications of Information Technology (EAIT)

Reviewer

IEEE Symposium on Computer Applications&Industrial Electronics (ISCAIE2018), Penang Island

Reviewer

Fourth International Symposium on Signal Processing and Intelligent Recognition Systems (S

Reviewer
2018

IEEE Conference on Applied Signal Processing (ASPCON 2018), Kolkata

Reviewer
2019

10th IEEE Control and System Graduate Research Colloquium (IEEE ICSGRC 2019), Malaysia

Reviewer

15th IEEE Colloquium on Signal Processing and its Applications (IEEE CSPA 2019), Penang, M

Reviewer

4th 2019 IEEE International Conference on Automatic Control and Intelligent Systems (IEEE

Reviewer
2019

23rd International Symposium on VLSI Design and Test (VDAT-2019)

Reviewer
2015

IEEE International Conference on Advanced Networks and Telecommunications Systems (ANTS)

Session Chair
2017

IEEE Region 10 Conference (TENCON), Penang, Malaysia

Session Chair

International Conference on Computational Intelligence in Pattern Recognition (CIPR), IIES

Session Chair
2019

IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Miami, Florida

Session Chair

Institute of Electrical and Electronics Engineers (IEEE)

Member

IEEE Computer Society

Member

IEEE Communications Society

Member

The Institution of Electronics and Telecommunication Engineers (IETE)

Fellow - Life Member

Bio

Computer Organization and Architecture, Reconfigurable Computing, Embedded Systems, Internet of Things (IoT), Computational Architecture for Next Generation Sequencing, Hardware Architecture for Network Routing Schemes

Personal Details

  • Male
  • Associate Professor , Indian Institute of Engineering Science & Technology, Shibpur (formerly Bengal Engineering & Science University)
  • Indian Institute of Engineering Science And Technology, Shibpur
Ph.D.
Jadavpur University 2017
M.E.
West Bengal University of Technology 2005
B.Tech.
Other Institute 2002
Associate Professor Feb 2019 – Present
Indian Institute of Engineering Science & Technology, Shibpur (formerly Bengal Engineering & Science University) | Department of Computer Science and Technology
Assistant Professor Sep 2013 – Feb 2019
Indian Institute of Engineering Science & Technology, Shibpur (formerly Bengal Engineering & Science University) | Department of Computer Science and Technology
Assistant Professor Apr 2008 – Sep 2013
West Bengal University of Technology
Assistant Professor Aug 2006 – Mar 2008
Jalpaiguri Government Engineering College

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Co-Authors (2)

Ashish Kumar

Prof Ashish Kumar Layek

Indian Institute of Engineering Science & Technology, Shibpur (formerly Bengal Engineering & Science University)

Bhaskar

Dr Bhaskar Sardar

Jadavpur University

Scholarly Work

Design and Implementation of a Comparison-Free Scalable High-Throughput Energy-Efficient Hardware Sorting Engine for FPGA-Based Embedded System Applications

Funding Agency: Department of Science & Technology and Bio-Technology, Government of West Bengal

Principal Investigator

9.30 Lakhs

2019 - 2023

Completed
Design and Implementation of Pipeline Architecture for DNA Sequence Alignment

Funding Agency: Department of Bio-Technology (DBT), Ministry of Science and Technology, Government of India

Principal Investigator

20.44 Lakhs

2017 - 2020

Completed

Design of Pipelined Architecture for Biological Sequence Alignment

University Indian Institute of Engineering Science and Technology, Shibpur
Year 2024

Intelligent Associative Memory (IAM) System

S. Ghosh
Engineering and Technology Patent No. : 488100 Filed : 23-02-2023
Published : 10-03-2023 Granted

Scholarly Publications

SRAM based longest prefix matching approach for multigigabit IP processing

Open Access
Conference Paper
Year: 2016. Volume: 2016-February .
Authors: Ray S.S.;Ghosh S.;Sardar B.
DOI 10.1109/ANTS.2015.7413624
3 1

A scalable high-throughput pipeline architecture for DNA sequence alignment

Open Access
Conference Paper
Year: 2016. Volume: 2016-January .
Authors: Ghosh S.;Mandal S.;Saha Ray S.
DOI 10.1109/TENCON.2015.7373055
4 4

A fast range matching architecture with unit storage expansion ratio and high memory utilization using SBiCAM for packet classification

Open Access
Conference Paper
Year: 2015.
Authors: Ray S.S.;Bhattacharya A.;Ghosh S.
DOI 10.1109/INDICON.2014.7030357
1

A novel approach for prefix minimization using Ternary Trie (PMTT) for packet classification

Open Access
Conference Paper
Year: 2015. Volume: 2015-January .
Authors: Ray S.S.;Chatterjee A.;Ghosh S.
DOI 10.1109/TENCON.2014.7022466

Low-cost hierarchical memory-based pipelined architecture for DNA sequence matching

Open Access
Conference Paper
Year: 2015.
Authors: Ray S.S.;Ghosh S.;Prasad R.
DOI 10.1109/INDICON.2014.7030681
3 8

High through-put scalable query processing architecture using STCAM

Open Access
Conference Paper
Year: 2013.
Authors: Ghosh S.;Ray S.S.;Mandal S.
DOI 10.1109/ICCIC.2013.6724274

A hierarchical high-throughput and low power architecture for longest prefix matching for packet forwarding

Open Access
Conference Paper
Year: 2013.
Authors: Ray S.S.;Chatterjee A.;Ghosh S.
DOI 10.1109/ICCIC.2013.6724271
7 9

Smart Ternary Content Addressable Memory (STCAM) architecture

Open Access
Conference Paper
Year: 2012. Pages: 434-438 .
Authors: Ray S.S.;Ghosh S.
DOI 10.1109/ICACCCT.2012.6320817
3