Dr Janakiraman Viraraghavan

vidwan id: 67635

Male

Assistant Professor, Department of Electrical Engineering
Indian Institute of Technology Madras

0000-0003-4899-0368 Google Scholar Icon

24473767200

Expertise

Electrical and Electronic Engineering

Publications

Total Articles 17

Books 0

Proceedings 0

Publications

Scopus

Citations 114

h-index 7

CrossRef

Citations 80

h-index 6

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Bio

Machine Learning Algorithms on Hardware, Statistical Analysis in VLSI

Personal Details

Male
Assistant Professor , Indian Institute of Technology Madras
Indian Institute Of Technology, Chennai, Tamil Nadu, India

Ph.D

Indian Institute of Science Bangalore 2010

Assistant Professor Nov 2016 – Present

Indian Institute of Technology Madras | Department of Electrical Engineering

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Dr N PRAKASH

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Mr Mrinmoy Sadhukhan

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Dr Bharadwaj Satchidanandan

Assistant Professor

B S Murty

Chair Professor

Dr Sriram Balasubramanian

Assistant Professor

Prof Prasad Patnaik B S V

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Co-Authors (3)

Prof Bharadwaj Amrutur

Indian Institute of Science Bangalore

Dr BISHNU PRASAD DAS

Indian Institute of Technology Roorkee

Prof Bijoy Krishna Das

Indian Institute of Technology Madras

Scholarly Work

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Scholarly Publications

Flash based in-memory multiply-accumulate realisation: A theoretical study

Open Access

Conference Paper

Year: 2020. Volume: 2020-October .

Authors: Ashwin Balagopal S.;Viraraghavan J.

80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory with No Added Process Complexity

Open Access

Article

Year: 2018. Volume: 53 , Issue: 3 , Pages: 949-960 .

Authors: Jayaraman B.;Leu D.;Viraraghavan J.;Cestero A.;Yin M.;Golz J.;Tummuru R.R.;Raghavan R.;Moy D.;Kempanna T.;Khan F.;Kirihata T.;Iyer S.S.

10.1109/JSSC.2017.2784760

A 14 nm 1.1 Mb embedded DRAM macro with 1 ns access

Open Access

Article

Year: 2016. Volume: 51 , Issue: 1 , Pages: 230-239 .

Authors: Fredeman G.;Plass D.W.;Mathews A.;Viraraghavan J.;Reyer K.;Knips T.J.;Miller T.;Gerhard E.L.;Kannambadi D.;Paone C.;Lee D.;Rainey D.J.;Sperling M.;Whalen M.;Burns S.;Tummuru R.R.;Ho H.;Cestero A.;Arnold N.;Khan B.A.;Kirihata T.;Iyer S.S.

10.1109/JSSC.2015.2456873

80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity

Open Access

Conference Paper

Year: 2016. Volume: 2016-September .

Authors: Viraraghavan J.;Leu D.;Jayaraman B.;Cestero A.;Kilker R.;Yin M.;Golz J.;Tummuru R.R.;Raghavan R.;Moy D.;Kempanna T.;Khan F.;Kirihata T.;Iyer S.