Ministry of Education
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Dr Saurabh Saxena

vidwan id: 67629
Male

Assistant Professor, Department of Electrical Engineering
Indian Institute of Technology Madras

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Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 50
Books 0
Proceedings 0

Publications

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Scopus

Citations 694
h-index 14

CrossRef

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Citations 445
h-index 12
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Professional Recognition

2018

Early Career Research Award

Science and Engineering Research Board, Dept. of Science & Technology

Community & Membership

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Bio

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Personal Details

  • Male
  • Assistant Professor , Indian Institute of Technology Madras
  • Indian Institute Of Technology, Chennai, Tamil Nadu, India
Ph.D
Other Institute 2015
Assistant Professor Mar 2016 – Present
Indian Institute of Technology Madras | Department of Electrical Engineering

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Co-Authors (3)

Prerna

Dr Prerna Saxena

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Scholarly Work

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AUTO RECONFIGURABLE MULTI-PHASE VOLTAGE REGULATOR

INDIAN INSTITUTE OF TECHNOLOGY MADRAS
- Patent No. : IN201841033933A Filed : 10-09-2018
Published : 13-03-2020 Published

Scholarly Publications

A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver

Open Access
Article
Year: 2017. Volume: 52 , Issue: 5 , Pages: 1399-1411 .
Authors: Saxena S.;Shu G.;Nandwana R.K.;Talegaonkar M.;Elkholy A.;Anand T.;Choi W.S.;Hanumolu P.K.
DOI 10.1109/JSSC.2016.2645738
14 16

A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS

Open Access
Article
Year: 2017. Volume: 52 , Issue: 9 , Pages: 2306-2320 .
Authors: Talegaonkar M.;Anand T.;Elkholy A.;Elshazly A.;Nandwana R.K.;Saxena S.;Young B.;Choi W.S.;Hanumolu P.K.
DOI 10.1109/JSSC.2017.2718670
7 10

A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS

Open Access
Conference Paper
Year: 2017. Volume: 60 , Pages: 492-493 .
Authors: Nandwana R.;Saxena S.;Elkholy A.;Talegaonkar M.;Zhu J.;Choi W.;Elmallah A.;Hanumolu P.
DOI 10.1109/ISSCC.2017.7870476
8 12

A 1-to-2048 fully-integrated cascaded digital frequency synthesizer for low frequency reference clocks using scrambling TDC

Open Access
Article
Year: 2017. Volume: 64 , Issue: 2 , Pages: 283-295 .
Authors: Nandwana R.K.;Saxena S.;Elshazly A.;Mayaram K.;Hanumolu P.K.
DOI 10.1109/TCSI.2016.2609855
8 11

A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL with Extended Range Multi-Modulus Divider

Open Access
Article
Year: 2016. Volume: 51 , Issue: 8 , Pages: 1771-1784 .
Authors: Elkholy A.;Saxena S.;Nandwana R.K.;Elshazly A.;Hanumolu P.K.
DOI 10.1109/JSSC.2016.2557807
56 75

A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS

Open Access
Conference Paper
Year: 2016. Volume: 59 , Pages: 398-399 .
Authors: Shu G.;Choi W.S.;Saxena S.;Kim S.J.;Talegaonkar M.;Nandwana R.;Elkholy A.;Wei D.;Nandi T.;Hanumolu P.K.
DOI 10.1109/ISSCC.2016.7418075
3 12

A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition

Open Access
Article
Year: 2016. Volume: 51 , Issue: 2 , Pages: 428-439 .
Authors: Shu G.;Choi W.S.;Saxena S.;Talegaonkar M.;Anand T.;Elkholy A.;Elshazly A.;Hanumolu P.K.
DOI 10.1109/JSSC.2015.2497963
55 81

A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links

Open Access
Article
Year: 2015. Volume: 50 , Issue: 12 , Pages: 3101-3119 .
Authors: Anand T.;Talegaonkar M.;Elkholy A.;Saxena S.;Elshazly A.;Hanumolu P.K.
DOI 10.1109/JSSC.2015.2470553
14 14