Ministry of Education
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Dr Nagendra Krishnapura

vidwan id: 61882
Male

Associate Professor, Department of Electrical Engineering
Indian Institute of Technology Madras

Orchid Icon 0000-0002-8429-8910 Google Scholar Icon 6602718407

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 83
Books 0
Proceedings 0

Publications

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Scopus

Citations 1059
h-index 17

CrossRef

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Citations 699
h-index 13
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Professional Recognition

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Community & Membership

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Bio

Microelectronics, VLSI, MEMS

Personal Details

  • Male
  • Associate Professor , Indian Institute of Technology Madras
  • Indian Institute Of Technology, Madras, Tamil Nadu, India
Ph.D
Other Institute 2000
Associate Professor Jun 2010 – Present
Indian Institute of Technology Madras | Department of Electrical Engineering
Assistant Professor Jun 2005 – Jun 2010
Indian Institute of Technology Madras | Department of Electrical Engineering

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Co-Authors (12)

Amitava Das

Amitava Das Gupta

Indian Institute of Technology Madras

Anand

Mr Anand Lokapure

National Institute of Oceanography

Aniruddhan

Dr Aniruddhan S

Indian Institute of Technology Madras

Anil

Anil Prabhakar

Indian Institute of Technology Madras

Ashwin Kumar

Dr Ashwin Kumar R S

Indian Institute of Technology Kanpur

Chithra

Dr Chithra .

Indian Institute of Technology Kanpur

Imon

Dr Imon Mondal

Indian Institute of Technology Kanpur

Manas

Dr Manas Maity

Visva-Bharati University

Chakravarthy

Dr Chakravarthy Mathiazhagan

Indian Institute of Technology Madras

Nitin

Dr Nitin Chandrachoodan

Indian Institute of Technology Madras

Shanthi

Dr Shanthi Pavan

Indian Institute of Technology Madras

Yujendra

Prof Yujendra Mitikiri

Indian Institute of Technology, Tirupati

Scholarly Work

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Wideband tunable true-time-delay architecture using a Variable order all-pass filter and its applications to Continuous-time pulse processing

University Indian Institute of Technology Madras
Year 2018

LOW PHASE NOISE QUADRATURE OSCILLATORS

INDIAN INSTITUTE OF TECHNOLOGY MADRAS ( INDIAN INSTITUTE OF TECHNOLOGY MADRAS)
- Patent No. : IN201741033376A Filed : 20-09-2017
Published : 22-03-2019 Published

A METHOD OF PRODUCING A LINEAR CURRENT SIGNAL IN A BASEBAND VOLTAGE-TOCURRENT (V-I) CONVERTER

INDIAN INSTITUTE OF TECHNOLOGY MADRAS
- Patent No. : IN201402897I4 Filed : 13-06-2014
Published : 29-01-2016 Published

METHOD FOR DETERMINING DISTORTION CONTRIBUTION OF INDIVIDUAL ELEMENTS IN AN ANALOG CIRCUIT

INDIAN INST TECHNOLOGY MADRAS | INDIAN INSTITUTE OF TECHNOLOGY MADRAS
- Patent No. : IN201304325I4 Filed : 24-09-2013
Published : 28-08-2015 Published

Scholarly Publications

Linearity- and Gain-Enhanced Wideband Transconductor Using Digitally Auto-Tuned Negative Conductance Load

Open Access
Conference Paper
Year: 2018. Volume: 2018-May .
Authors: Mondal I.;Krishnapura N.
DOI 10.1109/ISCAS.2018.8351317
2 2

Low 1/f3 Phase Noise Quadrature LC VCOs

Open Access
Article
Year: 2018. Volume: 65 , Issue: 7 , Pages: 2127-2138 .
Authors: Bhat A.;Krishnapura N.
DOI 10.1109/TCSI.2017.2782247
15 17

Reset-free memoryless delta-sigma analog-to-digital conversion

Open Access
Article
Year: 2018. Volume: 65 , Issue: 11 , Pages: 3651-3661 .
Authors: Kumar R.S.A.;Behera D.;Krishnapura N.
DOI 10.1109/TCSI.2018.2854707
11 12

Expansion and compression of analog pulses by bandwidth scaling of continuous-time filters

Open Access
Article
Year: 2018. Volume: 65 , Issue: 9 , Pages: 2703-2714 .
Authors: Mondal I.;Krishnapura N.
DOI 10.1109/TCSI.2018.2799080
2 4

A Low Power Multi-channel Input Delta-Sigma ADC without Reset

Open Access
Conference Paper
Year: 2017. Pages: 9-14 .
Authors: Kumar A.;Behera D.;Krishnapura N.
DOI 10.1109/VLSID.2017.85

Optimum scaling of stages in a frequency divider chain for best jitter FoM

Open Access
Conference Paper
Year: 2017.
Authors: Kumar S.;Krishnapura N.
DOI 10.1109/ISCAS.2017.8051001
1 1

Session 12-Analog techniques i

Open Access
Editorial
Year: 2017. Volume: 2017-April .
Authors: Krishnapura N.;Suyama K.
DOI 10.1109/CICC.2017.7993608

A 2-GHz Bandwidth, 0.25-1.7 ns True-Time-Delay Element Using a Variable-Order All-Pass Filter Architecture in 0.13 \mu m CMOS

Open Access
Article
Year: 2017. Volume: 52 , Issue: 8 , Pages: 2180-2193 .
Authors: Mondal I.;Krishnapura N.
DOI 10.1109/JSSC.2017.2693229
65 78