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Dr Kuleen Kumar

vidwan id: 609331
Male

Assistant Professor (Grade-II), Department of Electronics and Communication Engineering
National Institute of Technology, Puducherry

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 20
Books 0
Proceedings 0

Publications

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Scopus

Citations 68
h-index 5

CrossRef

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Citations 40
h-index 4
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Professional Recognition

2021

Best Paper Award

Advances in Electrical, Computing, Communications and Sustainable Technologies (ICAECT 2021), IEEE
2024

Best Paper Award

International Conference on Semiconductor Materials and Manufacturing Technology 2024 (ICSMMT 2024)

Community & Membership

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Bio

Nano system device technology:Semiconductor Device Modelling (DGFET, FinFET, Nanowires, Nanosheets), Thin-Film Transistor (TFT), Semiconductor sensors integration with IoT.

Personal Details

  • Male
  • Assistant Professor (Grade-II) , National Institute of Technology, Puducherry
Ph.D
Other Institute 2022
Assistant Professor (Grade-II) Jan 2025 – Present
National Institute of Technology, Puducherry | Department of Electronics and Communication Engineering
Post-Doctoral Fellow Feb 2024 – Jan 2025
Indian Institute of Technology Guwahati
Guest Faculty Sep 2022 – Jun 2023
Mizoram University

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Abhishek

Mr Abhishek Shukla

Assistant Professor (Grade-I)

N

Dr N PRAKASH

Assistant Professor

Mrinmoy

Mr Mrinmoy Sadhukhan

Research Scholar

Haranath

Mr Haranath Rakshit

Junior Research Fellow

Organisations (68+)

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BABU

Dr BABU S

Officer

Ashok Kumar

Dr Ashok Kumar T

Assistant Professor

Balakumar

Dr Balakumar Vaithilingam

Assistant Professor

Bidwan

Dr Bidwan Chakraborty

Assistant Professor

Bijukumar

Dr Bijukumar B

Assistant Professor

Aniruddha

Dr Aniruddha Kanhe

Associate Professor

Ansuman

Dr Ansuman Mahapatra

Assistant Professor

Ajay Kumar

Dr Ajay Kumar Mishra

Associate Professor

Johnney Mertens

Dr Johnney Mertens A

Assistant Professor

Co-Authors (3)

Rajesh

Dr Rajesh Dey

Gopal Narayan Singh University, Jamuhar

Rudra Sankar

Dr Rudra Sankar Dhar

National Institute of Technology Mizoram

Shanmugaraja

Mr Shanmugaraja T

KPR Institute of Engineering and Technology

Scholarly Work

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AN UNDERLAP INDUCED NANO SYSTEM WITH STRAINED-SI CHANNEL BASED DOUBLE GATE NANO-FIELD EFFECT TRANSISTOR (DGFET)

National Institute of Technology Mizoram
Engineering and Technology Patent No. : 2023/02597 Filed : 27-02-2023
Published : 31-05-2023 Granted

A NANOSYSTEM-BASED DEVICE USING ULTRA-THIN TRI-LAYERED HOI CHANNEL WITH INCREASED DRIVE CURRENTS IN RECTANGULAR GATE

National Institute of Technology Mizoram
Engineering and Technology Patent No. : 2023/02841 Filed : 27-02-2023
Published : 31-05-2023 Granted

A NANOWIRE SYSTEM FOR FASTER SWITCHING WITH ENHANCED ON-CURRENT AND ITS PREPARING PROCESS THEREOF

National Institute of Technology Mizoram
Engineering and Technology Patent No. : 2023/02847 Filed : 27-02-2023
Published : 31-05-2023 Granted

A NANO-DEVICE USING ULTRA-THIN TRI-LAYERED STRAINED-CHANNEL FOR ENHANCING DRIVE CURRENTS IN TRI–GATE FIN-FET ARCHITECTURE

National Institute of Technology Mizoram
Engineering and Technology Patent No. : 2023/02593 Filed : 27-02-2023
Published : 31-05-2023 Granted

A NANO-COMPOSITES BASED SMART MEMBRANE DEVICE WITH ENHANCED PERFORMANCE AND ITS PREPARATION PROCESS THEREOF

National Institute of Technology Mizoram
Engineering and Technology Patent No. : 2021105410 Filed : 13-08-2021
Published : 27-10-2021 Granted

A NANOSYSTEM DEVICE FOR FASTER SWITCHING WITH REDUCED LEAKAGE AND ITS PREPARING PROCESS THEREOF

National Institute of Technology Mizoram
Engineering and Technology Patent No. : 2021105335 Filed : 11-08-2021
Published : 27-10-2021 Granted

A M-O-(SI/SIGE/SI) STRUCTURED DEVICE OF TRI-LAYERED NANOSYSTEM SEMICONDUCTOR AND ITS PROCESS THEREOF

National Institute of Technology Mizoram
Engineering and Technology Patent No. : 2021105085 Filed : 07-08-2021
Published : 20-04-2022 Granted

ULTRA-THIN COMPOSITE OF HETEROSEMICONDUCTOR ASSEMBLY LOADED ONTO OXIDE/METAL FORMING A FIVE-LAYERED DIELECTRIC BASED CAPACITIVE SYSTEM AT NANO REGIME

National Institute of Technology Mizoram
- Patent No. : 528098 Filed : 07-12-2020
Published : 15-03-2024 Granted

Scholarly Publications

Design of DG MOSFET with Tri-Layered Strained Silicon Channel

Open Access
Conference Paper

Development of 14nm Tri-layered (s-Si/s-SiGe/s-Si) Channel DG- NanoFET

Open Access
Conference Paper
Authors: Kumar K.;Sankar Dhar R.

Design of double gate nano-FET

Open Access
Conference Paper
Authors: Kumar K.;Khiangte L.;Dhar R.S.

Design of 2-bit parallel asynchronous self-timed adder and 2-bit parallel adder using radix adder

Open Access
Conference Paper