Ministry of Education
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Dr Manjith B C

vidwan id: 594845
Female

Assistant Professor (Grade-I), Department of Computer Science and Engineering - Cyber Security
Indian Institute of Information Technology, Kottayam

Orchid Icon 0000-0002-6131-907X Google Scholar Icon 57204588175

Expertise

  • Computer Science Cybernetics

Publications

Total Articles 10
Books 0
Proceedings 0

Publications

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Scopus

Citations 40
h-index 3

CrossRef

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Citations 30
h-index 2
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Professional Recognition

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Community & Membership

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Bio

Computer Science and Engineering, Cyber Security

Personal Details

  • Female
  • Assistant Professor (Grade-I) , Indian Institute of Information Technology, Kottayam
  • Department of Computer Science and Engineering - Cyber Security, Indian Institute of Information Technology Kottayam
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Assistant Professor (Grade-I) Jun 2020 – Present
Indian Institute of Information Technology, Kottayam | Department of Computer Science and Engineering - Cyber Security

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Co-Authors (3)

Dhanalakshmi

Dr Dhanalakshmi R

Indian Institute of Information Technology, Srirangam

Kokila

Dr Kokila Jagadeesh

Indian Institute of Information Technology, Srirangam

N

Prof N Ramasubramanian

National Institute of Technology Tiruchirappalli

Scholarly Work

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Scholarly Publications

Enabling self-adaptability of small scale and large scale security systems using dynamic partial reconfiguration

Open Access
Article
Journal of Ambient Intelligence and Humanized Computing. Year: 2021. Volume: 12 , Issue: 10 , Pages: 9387-9403 .
Authors: Manjith B.C.;Dhanalakshmi R.
DOI 10.1007/s12652-020-02658-9
1 2

Securing AES accelerator from key-leaking trojans on FPGA

Open Access
Article
Year: 2020. Volume: 11 , Issue: 3 , Pages: 84-105 .
Authors: Manjith B.C.;Ramasubramanian N.
DOI 10.4018/IJERTCS.2020070105
2 3

Improving correctness of logic circuit using self-healing built-in logic test module in FPGA using dynamic partial reconfiguration

Open Access
Article
Year: 2019. Volume: 8 , Issue: 2 , Pages: 2024-2034 .
Authors: Manjith B.C.
DOI 10.35940/ijrte.B2104.078219

Correction to: AES Hardware Accelerator on FPGA with Improved Throughput and Resource Efficiency (Arabian Journal for Science and Engineering, (2018), 43, 12, (6873-6890), 10.1007/s13369-017-2925-0)

Open Access
Erratum
Arabian Journal for Science and Engineering. Year: 2019. Volume: 44 , Issue: 3 , Pages: 2861 .
Authors: Baby Chellam M.;Natarajan R.
DOI 10.1007/s13369-018-3095-4
1 1

Hardware evolution of AES algorithm on FPGA

Open Access
Conference Paper
Year: 2019.
Authors: Manjith B.C.
DOI 10.1109/i-PACT44901.2019.8960105

Improving overall parallelism in AES accelerator using BRAM and multiple input blocks

Open Access
Conference Paper
Year: 2019.
Authors: Manjith B.C.
DOI 10.1109/i-PACT44901.2019.8960016
3 3

Cryptographic engines for cloud based on FPGA

Open Access
Book Chapter
Year: 2019. Pages: 273-308 .
Authors: Natarajan R.;Chellam M.B.
DOI 10.1049/pbse009e_ch11

AES Hardware Accelerator on FPGA with Improved Throughput and Resource Efficiency

Open Access
Article
Arabian Journal for Science and Engineering. Year: 2018. Volume: 43 , Issue: 12 , Pages: 6873-6890 .
Authors: Baby Chellam M.;Natarajan R.
DOI 10.1007/s13369-017-2925-0
21 26