Ministry of Education
Vidvan Image

Dr C Pakkiraiah

vidwan id: 568617
Male

Assistant Professor, Department of Technology
The Apollo University

Orchid Icon 0000-0003-4826-1640 Google Scholar Icon 57477336500 Google Scholar Icon 208-k1oAAAAJ

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 16
Books 0
Proceedings 0

Publications

No publication activity to display at the moment.

Scopus

Citations 11
h-index 2

CrossRef

CrossRef Icon
Citations 6
h-index 1
Google Scholar

Loading Scholar statistics...

Professional Recognition

2024

Best Researcher Award

International Asia Research Aaward
2014

Gold Medal

Sri Vidyanikhetan Educational Trust

Community & Membership

No Data Found

There is currently nothing to display here.

American Chamber Of Research

2024
Life time

International Association of Engineers

2022
Life time

Bio

VLSI Design, Quantum Computing

Personal Details

  • Male
  • Assistant Professor , The Apollo University
  • Department of Technology, Apollo University
PhD
Sri Venkateswara University 2024
Assistant Professor Aug 2024 – Present
The Apollo University | Department of Technology
Assistant Professor Oct 2022 – Aug 2024
Sri Vasavi Institute of Engineering & Technology, Nandamuru, Pedana Mandal | ECE
Assistant Professor Jun 2019 – Oct 2019
Rajeev Gandhi Memorial College of Engineering & Technology, Nandyal | Department of Electronics and Communication Engineering
Assistant Professor Jun 2013 – Dec 2017
Annamacharya Institute of Technology And Sciences, Chinthakomma Dinne | Department of Electronics and Communication Engineering

Related Profiles

Experts (19623+)

View All
Pragati

Ms Pragati Mishra

Assistant Professor

Sridhar

Dr Sridhar Sekar

Assistant Professor

DEEPAK

Mr DEEPAK B N

N/A

Md

Dr Md Nadeem M

Assistant Professor

Rashmi

Rashmi Chandra

Assistant Professor

Anjali

Dr Anjali Jadhav

Doctor

Abhishek

Mr Abhishek Shukla

Assistant Professor (Grade-I)

N

Dr N PRAKASH

Assistant Professor

Mrinmoy

Mr Mrinmoy Sadhukhan

Research Scholar

Haranath

Mr Haranath Rakshit

Junior Research Fellow

Organisations (62+)

View All
Bedaduri

Mr Bedaduri Ramamurthy

Guest Faculty

Aswin

Mr Aswin Sugunan

Assistant Professor

Asha

Dr Asha P Johnson

Assistant Professor

Nageswara Rao

Dr Nageswara Rao Bendi

Associate Professor

Bhargavi

Dr Bhargavi Maram

Assistant Professor

Bhaskar Reddy

Dr Bhaskar Reddy Kesavan

Dean

Anwesha

Ms Anwesha Paul

Lecturer

A B

Dr A B Manju

Assistant Professor

Adlin K

Adlin K Kazia

Lecturer

Akhil

Mr Akhil J

Lecturer

Co-Authors (0)

no data found

Scholarly Work

No Data Found

There is currently nothing to display here.

No Data Found

There is currently nothing to display here.

No Data Found

There is currently nothing to display here.

Scholarly Publications

Design and FPGA Realization of Energy Efficient Reversible Full Adder for Digital Computing Applications

Open Access
Article
Journal of VLSI circuits and systems. Year: 2024. Volume: 6 , Issue: 1 , Pages: 7-18 .
Authors: Pakkiraiah C.;Satyanarayana R.V.S.
DOI 10.31838/jvcs/06.01.02
4

Design of Low Power Modular (x mod p) Reduction Unit Based on Switching Activity for Data Security Applications

Open Access
Conference Paper
Year: 2023. Volume: 962 , Pages: 13-25 .
Authors: C. Pakkiraiah ., R. V. S. Satyanarayana .,
DOI 10.1007/978-981-19-6780-1_2
1

Design of Low Power Artificial Hybrid Adder using Neural Network Classifiers to Minimize Energy Delay Product for Arithmetic Application

Open Access
article
Year: 2022. Volume: 184 , Pages: 1--8 .
Authors: C. Pakkiraiah, R.V.S. Satyanarayana

FPGA REALIZATION OF LOW POWER MULTI LAYER PERCEPTRON FULL ADDER TO MINIMIZE EDP OF MODULAR MULTIPLIER

Open Access
article
Year: 2022. Volume: 10 , Pages: 1--12 .
Authors: Pakkiraiah C, Dr. R V S. Satyanarayana

Design of low power full adder using multilayer perceptron to minimize energy delay product of computational logic circuits

Open Access
article
Year: 2022. Volume: 15 , Pages: 42--58 .
Authors: Pakkiraiah, C and Satyanarayana, RVS

Design of Low Power Modular (x mod p) Reduction Unit Based on Switching Activity for Data Security Applications

Open Access
incollection
Year: 2022. Pages: 13--25 .
Authors: Pakkiraiah, C and Satyanarayana, RVS

Design and FPGA realization of an energy efficient artificial neural modular exponentiation architecture

Open Access
inproceedings
Year: 2022. Pages: 115--126 .
Authors: Pakkiraiah, Ch and Satyanarayana, RVS

Design and FPGA Realization of an Energy Efficient Artificial Neural Modular Exponentiation Architecture

Open Access
Conference Paper
Year: 2022. Volume: 1729 CCIS , Pages: 115-126 .
Authors: C. Pakkiraiah ., R. V. S. Satyanarayana .,
DOI 10.1007/978-3-031-21750-0_10
1 1