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Dr C Pakkiraiah

vidwan id: 568617
Male

Assistant Professor, Department of Technology
The Apollo University

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 16
Books 0
Proceedings 0

Publications

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Scopus

Citations 11
h-index 2

CrossRef

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Citations 6
h-index 1
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Professional Recognition

2024

Best Researcher Award

International Asia Research Aaward
2014

Gold Medal

Sri Vidyanikhetan Educational Trust

Community & Membership

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American Chamber Of Research

2024
Life time

International Association of Engineers

2022
Life time

Bio

VLSI Design, Quantum Computing

Personal Details

  • Male
  • Assistant Professor , The Apollo University
  • Department of Technology, Apollo University
PhD
Sri Venkateswara University 2024
Assistant Professor Aug 2024 – Present
The Apollo University | Department of Technology
Assistant Professor Oct 2022 – Aug 2024
Sri Vasavi Institute of Engineering & Technology, Nandamuru, Pedana Mandal | ECE
Assistant Professor Jun 2019 – Oct 2019
Rajeev Gandhi Memorial College of Engineering & Technology, Nandyal | Department of Electronics and Communication Engineering
Assistant Professor Jun 2013 – Dec 2017
Annamacharya Institute of Technology And Sciences, Chinthakomma Dinne | Department of Electronics and Communication Engineering

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Co-Authors (0)

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Scholarly Work

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Scholarly Publications

Design and FPGA Realization of Energy Efficient Reversible Full Adder for Digital Computing Applications

Open Access
Article

Design of Low Power Modular (x mod p) Reduction Unit Based on Switching Activity for Data Security Applications

Open Access
Conference Paper
Authors: C. Pakkiraiah ., R. V. S. Satyanarayana .,

Design of Low Power Artificial Hybrid Adder using Neural Network Classifiers to Minimize Energy Delay Product for Arithmetic Application

Open Access
article
Authors: C. Pakkiraiah, R.V.S. Satyanarayana

FPGA REALIZATION OF LOW POWER MULTI LAYER PERCEPTRON FULL ADDER TO MINIMIZE EDP OF MODULAR MULTIPLIER

Open Access
article
Authors: Pakkiraiah C, Dr. R V S. Satyanarayana

Design of low power full adder using multilayer perceptron to minimize energy delay product of computational logic circuits

Open Access
article
Authors: Pakkiraiah, C and Satyanarayana, RVS

Design of Low Power Modular (x mod p) Reduction Unit Based on Switching Activity for Data Security Applications

Open Access
incollection
Authors: Pakkiraiah, C and Satyanarayana, RVS

Design and FPGA realization of an energy efficient artificial neural modular exponentiation architecture

Open Access
inproceedings
Authors: Pakkiraiah, Ch and Satyanarayana, RVS

Design and FPGA Realization of an Energy Efficient Artificial Neural Modular Exponentiation Architecture

Open Access
Conference Paper
Authors: C. Pakkiraiah ., R. V. S. Satyanarayana .,