Ministry of Education
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Dr Arindam Banerjee

vidwan id: 551389
Male

Associate Professor, Faculty of Science and Technology
ICFAI University, Tripura

Orchid Icon 0000-0002-5982-8983 Google Scholar Icon 55186131600

Expertise

  • Telecommunications

Publications

Total Articles 27
Books 0
Proceedings 0

Publications

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Scopus

Citations 238
h-index 7

CrossRef

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Citations 74
h-index 5
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Community & Membership

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Bio

Electronics And Communication Engineering With Specialization In Vlsi Design, Embedded Systems And Iot

Personal Details

  • Male
  • Associate Professor , ICFAI University, Tripura
  • Faculty of Science and Technology, ICFAI University, Tripura
PhD
Other Institute 2019
Associate Professor Jan 2023 – Present
ICFAI University, Tripura | Faculty of Science and Technology

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Co-Authors (7)

Aniruddha

Mr Aniruddha Ghosh

JIS COLLEGE OF ENGINEERING 317

Anup

Prof Anup Dandapat

National Institute of Technology, Meghalaya

Arindam

Dr Arindam Banerjee

JIS COLLEGE OF ENGINEERING 317

Mainuck

Mr Mainuck Das

JIS COLLEGE OF ENGINEERING 317

Partha

Dr Partha Bhattacharyya

Indian Institute of Engineering Science & Technology, Shibpur (formerly Bengal Engineering & Science University)

Prabir Kumar

Dr Prabir Kumar Saha

National Institute of Technology, Meghalaya

Rajendra Kumar

Dr Rajendra Kumar Sharma

Jaypee University of Information Technology, Waknaghat

Scholarly Work

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Scholarly Publications

The design of reversible multiplier using ancient Indian mathematics

Open Access
Conference Paper
Year: 2013. Pages: 31-35 .
Authors: Banerjee A.;Das D.
DOI 10.1109/ISED.2013.13
3 4

Design of high speed Vedic multiplier for decimal number system

Open Access
book
Year: 2012. Volume: 7373 LNCS , Pages: 79-88 .
Authors: Saha, P.;Banerjee, A.;Dandapat, A.;Bhattacharyya, P.
2 12

ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics

Open Access
journal-article
Microelectronics Journal. Year: 2011. Volume: 42 , Issue: 12 , Pages: 1343-1352 .
Authors: Saha, P.;Banerjee, A.;Dandapat, A.;Bhattacharyya, P.
20 46

Vedic mathematics based 32-Bit multiplier design for high speed low power processors

Open Access
journal-article
International Journal on Smart Sensing and Intelligent Systems. Year: 2011. Volume: 4 , Issue: 2 , Pages: 268-284 .
Authors: Saha, P.;Banerjee, A.;Dandapat, A.;Bhattacharyya, P.
7

ASIC implementation of high speed processor for calculating discrete fourier transformation using circular convolution technique

Open Access
Article
WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS. Year: 2011. Volume: 10 , Issue: 8 , Pages: 278-288 .
Authors: Saha P.;Banerjee A.;Dandapat A.;Bhattacharyya P.
7

High speed ASIC design of complex multiplier using Vedic mathematics

Open Access
Conference Paper
Year: 2011. Pages: 237-241 .
Authors: Saha P.;Banerjee A.;Bhattacharyya P.;Dandapat A.
DOI 10.1109/TECHSYM.2011.5783852
76

Vedic divider: Novel architecture (ASIC) for high speed VLSI applications

Open Access
conference-paper
Year: 2011. Pages: 67-71 .
Authors: Saha, P.;Banerjee, A.;Bhattacharyya, P.;Dandapat, A.
8 16

Methodological approach in development of system design layout for alignment of a MSD collector for TWT application

Open Access
Conference Paper
Year: 2011. Pages: 501-502 .
Authors: Banerjee A.J.;Kumar B.S.;Sharma R.K.;Ghosh A.;Saha P.
DOI 10.1109/IVEC.2011.5747095