Ministry of Education
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Dr Jitesh Shinde

vidwan id: 536187
Male

Associate Professor, Electronics Engineering (VLSI Design & Technology)
CSMSS Chh. Shahu College of Engineering

Orchid Icon 0000-0003-3838-1921 Google Scholar Icon 55004008300 Google Scholar Icon 2T3WbvYAAAAJ

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 41
Books 0
Proceedings 0

Publications

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Scopus

Citations 104
h-index 4

CrossRef

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Citations 97
h-index 4
Google Scholar

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Professional Recognition

2021

International Edu-trainer Award 2020-21

International Institute of Organized Research (I2OR)
2020

AICTE Quality Improvement FDP Scheme , grant of 5,61,592 INR/- sanctioned

AICTE
2020

AICTE Quality Improvement FDP Scheme

AICTE
2020

AICTE MODROB on “Advanced Digital Signal Processing” for which grant obtained of 1259000/- INR obtained

AICTE
2020

Lib Migration Proposal

Scilab & IIT Bombay & sponsored by National Mission on Education through Information & Communication

Community & Membership

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Vigyan Bharti

2022
Lifetime

The Indian Society for Technical Education (ISTE)

2008
Life Member

Bio

Digital Signal Processing, Frontend And Backend Vlsi Design

Personal Details

  • Male
  • Associate Professor , CSMSS Chh. Shahu College of Engineering
  • Chh.Shahu College of Engineering Road, Kanchanwadi, Chhatrapati Sambhajinagar (Aurangabad), Maharashtra, India
Ph.D
Priyadarshini College of Engineering, Nagpur 2017
CDAC Diploma in VLSI Design
Other Institute 2008
M.Tech
Shri Ramdeobaba College of Engineering and Management, Nagpur 2007
Diploma
Other Institute 2007
B.Tech
Other Institute 2005
Associate Professor Jun 2024 – Present
CSMSS Chh. Shahu College of Engineering | Electronics Engineering (VLSI Design & Technology)
Associate Professor Oct 2023 – May 2024
Sandip University | School of Electrical and Electronics Engineering
Associate Professor Apr 2022 – Oct 2023
Cummins College of Engg for women,Nagpur
Assistant Professor Apr 2018 – Apr 2022
Vaagdevi College of Engineering
Assistant Professor May 2011 – Apr 2018
Priyadarshini J. L. College of Engineering Nagpur

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Co-Authors (4)

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Scholarly Work

Lib Migration Proposal

Funding Agency: Scilab & IIT Bombay & sponsored by National Mission on Education through Information & Communication Technology, under MHRD, Government of India

Principle Investigator

0

2019 - 2020

Completed
Design and Development of Vibration-based Energy Harvesting Devices for Wideband Low-Frequency Applications

Funding Agency: TEQIP-III, JNTUH

Co-principal Investigator

250,000

2019 - 2021

Completed
No Data Found

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MOUSE WITH STRESS DETECTION

Dr. Jitesh Ramdas Shinde
Dr. Rakesh Nayak
Engineering and Technology Patent No. : 384231-001 Filed : 18-04-2023
Published : 07-07-2023 Granted

IoT Based Face Mask And Body Temperature Sensing Device

Dr. Jitesh Shinde
Dr. RAKESH NAYAK
Engineering and Technology Patent No. : 37116-001 Filed : 29-09-2022
Published : 30-12-2022 Granted

A SMART FLOOR USING A TWO-PHASED TRIANGULAR PIEZOELECTRIC ENERGY HARVESTER

Dr. M. Krishnasamy
Dr. Jitesh Ramdas Shinde
- Application No. : 202141003266 A Filed : 23-01-2021
Published : 29-01-2021 Published

A SMART FLOOR USING A TWO-PHASED TRIANGULAR PIEZOELECTRIC ENERGY HARVESTER

Dr. M. Krishnasamy
Dr. Jitesh Ramdas Shinde
- Application No. : 202141003266 A Filed : 23-01-2021
Published : 29-01-2021 Published

A SMART FLOOR USING A TWO-PHASED TRIANGULAR PIEZOELECTRIC ENERGY HARVESTER

Dr. M. Krishnasamy
Dr. Jitesh Ramdas Shinde
- Application No. : 202141003266 A Filed : 23-01-2021
Published : 29-01-2021 Published

A SMART FLOOR USING A TWO-PHASED TRIANGULAR PIEZOELECTRIC ENERGY HARVESTER

Dr. M. Krishnasamy
Dr. Jitesh Ramdas Shinde
- Application No. : 202141003266 A Filed : 23-01-2021
Published : 29-01-2021 Published

A SMART FLOOR USING A TWO-PHASED TRIANGULAR PIEZOELECTRIC ENERGY HARVESTER

Dr. M. Krishnasamy
Dr. Jitesh Ramdas Shinde
- Application No. : 202141003266 A Filed : 23-01-2021
Published : 29-01-2021 Published

A SMART FLOOR USING A TWO-PHASED TRIANGULAR PIEZOELECTRIC ENERGY HARVESTER

Dr. M. Krishnasamy
Dr. Jitesh Ramdas Shinde
- Application No. : 202141003266 A Filed : 23-01-2021
Published : 29-01-2021 Published

A SMART FLOOR USING A TWO-PHASED TRIANGULAR PIEZOELECTRIC ENERGY HARVESTER

Dr. M. Krishnasamy
Dr. Jitesh Ramdas Shinde
- Application No. : 202141003266 A Filed : 23-01-2021
Published : 29-01-2021 Published

A SMART FLOOR USING A TWO-PHASED TRIANGULAR PIEZOELECTRIC ENERGY HARVESTER

Dr. M. Krishnasamy
Dr. Jitesh Ramdas Shinde
- Application No. : 202141003266 A Filed : 23-01-2021
Published : 29-01-2021 Published

A SMART FLOOR USING A TWO-PHASED TRIANGULAR PIEZOELECTRIC ENERGY HARVESTER

Dr. M. Krishnasamy
Dr. Jitesh Ramdas Shinde
Engineering and Technology Application No. : 202141003266A Filed : 23-01-2021
Published : 29-01-2021 Published

A SMART FLOOR USING A TWO-PHASED TRIANGULAR PIEZOELECTRIC ENERGY HARVESTER

Dr. M. Krishnasamy
Dr. Jitesh Ramdas Shinde
Engineering and Technology Application No. : 202141003266A Filed : 23-01-2021
Published : 29-01-2021 Published

DSD-PREDICT GENDER, AGE, COUNTRY AND MEANING: DETECT SOUND AND THEIR GENDER, AGE, COUNTRY AND MEANING USING DEEP LERNING

Dr. RAKESH NAYAK
Dr. JITESH RAMDAS SHINDE
- Application No. : 202041053285 A Filed : 08-12-2020
Published : 25-12-2020 Published

Scholarly Publications

Comprehensive Review on Comparative Analysis of FPGA & ASIC in Multi-objective Optimization of VLSI Circuit

Open Access
Year: 0000.
Authors: Jitesh Shinde, Shilpa Shinde;

Optimal multi-objective approach for VLSI implementation of digital FIR filters

Open Access
Year: 0000. Issue: 2470-74 .
Authors: Shinde, Jitesh; Salankar, S;

Multi-objective Optimization Approach for VLSI Implementation of FIR Filter

Open Access
Year: 0000. Volume: 6 , Issue: 108-120 .
Authors: Jitesh R Shinde , Suresh Salankar, Shilpa J Shinde;

Comparative Analysis Domino Logic Based Techniques For VLSI Circuit

Open Access
Year: 0000. Volume: 8 , Issue: 3803-3808 .
Authors: Shilpa Shinde, Jitesh Shinde;

VLSI Architecture for Neural Network

Open Access
Year: 0000.
Authors: Kumar, Dhananjay; Kumar, Dileep; Shinde, JR; Kumar, Amit; Kumar, Vineet;

Comprehensive Review on Comparative Analysis of FPGA & ASIC in Multi-objective Optimization of VLSI Circuit

Open Access
Year: 0000.
Authors: Jitesh Shinde, Shilpa Shinde;

Clock gating-A power optimizing technique for VLSI circuits

Open Access
Year: 0000. Issue: 16-18 .
Authors: Jitesh, Shinde; Salankar, SS;

An Optimization Design Strategy for Arithmetic Logic Unit

Open Access
Year: 0000. Volume: 1 , Issue: 1-13 .
Authors: JITESH ShINDE, SHILPA SHINDE;