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Dr Dineshkumar D

vidwan id: 534144
Male

Assistant Professor, Department of Electronics and Communication Engineering
Mepco Schlenk Engineering College, Virudhunagar

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 9
Books 0
Proceedings 0

Publications

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Scopus

Citations 11
h-index 2

CrossRef

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Citations 14
h-index 3
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Bio

VLSI Signal Processing, Analog VLSI.

Personal Details

  • Male
  • Assistant Professor , Mepco Schlenk Engineering College, Virudhunagar
  • Department of Electronics and Communication Engineering, Mepco Schlenk Engineering College
PhD
Other Institute 2023
Assistant Professor Jun 2012 – Present
Mepco Schlenk Engineering College, Virudhunagar | Department of Electronics and Communication Engineering

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Co-Authors (4)

Kirubakaran

Mr Kirubakaran G

Mepco Schlenk Engineering College, Virudhunagar

Shantha Selvakumari

Dr Shantha Selvakumari R

Mepco Schlenk Engineering College, Virudhunagar

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Scholarly Work

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Scholarly Publications

Performance analysis of multi-folded pipelined successive cancellation decoder architecture for polar code

Open Access
Article
Authors: Dinesh Kumar D ., Shantha Selvakumari R .,

Design and Thermal Analysis of Battery Thermal Management System for EV

Open Access
Conference Paper
Authors: Sadhasivam Deepan Kumar ., Vishnu Ramesh Kumar R ., Devadoss Dinesh Kumar ., R Manojkumar ., Tamilselvan A ., Boopathi M ., Lokesh C .,

Performance analysis of Min-Sum based LDPC decoder architecture for 5G new radio standards

Open Access
Conference Paper
Authors: D. Dinesh kumar ., R. Shantha Selvakumari .,

Damage detection in Aerospace structures using Chirped fiber Bragg grating

Open Access
Conference Paper
Authors: D. Dinesh kumar ., S. Sridhar raj ., V. Sivananth ., V. Ramkumar .,

Semi-parallel polar decoder architecture using shift-register-based partial-sum computation for 5G mobile communications

Open Access
Conference Paper
Authors: D.Dinesh kumar ., R.Shantha Selvakumari .,

Improving utilization rate of semi-parallel successive cancellation architecture for polar codes using 2-bit decoding

Open Access
Article
Authors: DINESH KUMAR DEVADOSS ., SHANTHA SELVA KUMARI RAMA PACKIAM .,

FPGA implementation of radix-2 based FFT architecture for real-valued signal processing

Open Access
Article

A 10-bit 150MS/s pipelined ADC with 2.5bit gain stage for high frequency applications

Open Access
Article