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Dr Satyendra Kumar

vidwan id: 532216
Male

Associate Professor, Department of Electronics and Communication Engineering
Jaypee Institute of Information Technology, Noida

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 34
Books 0
Proceedings 0

Publications

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Scopus

Citations 313
h-index 9

CrossRef

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Citations 312
h-index 9
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Professional Recognition

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Bio

VLSI Design: Semiconductor Memory Design, Design And Simulation Of Novel Semiconductor Devices

Personal Details

  • Male
  • Associate Professor , Jaypee Institute of Information Technology, Noida
  • Department of Electronics and Communication Engineering, Jaypee Institute of Information Technology, Noida
PhD
Other Institute 2018
Associate Professor Jan 2010 – Present
Jaypee Institute of Information Technology, Noida | Department of Electronics and Communication Engineering

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Co-Authors (6)

Abhishek

Dr Abhishek Kashyap

Jaypee Institute of Information Technology, Noida

Kapil Dev

Dr Kapil Dev Tyagi

Jaypee Institute of Information Technology, Noida

P. N.

Dr P. N. Kondekar

Pt. Dwarka Prasad Mishra Indian Institute of Information Technology Design & Manufacturing

Priyanka

Priyanka Verma

Noida Institute of Engineering and Technology, Greater Noida

Shamim

Dr Shamim Akhter

Jaypee Institute of Information Technology, Noida

Shivendra

Dr Shivendra Yadav

S.V. National Institute of Technology

Scholarly Work

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Design and Performance Investigation of Tunnel Field Effect Transistor and Its Applications

University Jaypee Institute of Information Technology, Noida, U.P., India
Year 2022

Design and Performance Analysis of Tunnel Field Effect Transistor and its Applications

University Jaypee Institute of Information Technology, Noida, U.P., India
Year 2023
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Scholarly Publications

Mole Fraction and Device Reliability Analysis of Vertical-Tunneling-Attributed Dual-Material Double-Gate Heterojunction-TFET with Si<inf>0.7</inf>Ge<inf>0.3</inf> Source Region at Device and Circuit Level

Open Access
Article

Investigation of In<inf>0.7</inf>Ga<inf>0.3</inf>As/Ga<inf>0.5</inf>As<inf>0.5</inf>Sb-Based Heterojunction TFET with Ferroelectric Gate Dielectric for Performance and Reliability<sup>∗</sup>

Open Access
Article

Simulation-Based Study of Gaussian-Doped Channel in Stacked Gate Oxide MOS Transistor

Open Access
Conference Paper

Reduction of Subthreshold Leakage Using Metal Strip in SGO Double-Gate MOSFET

Open Access
Conference Paper
Authors: Bhaumik A.S.;Kumar S.;Chaturvedi S.;Singh K.S.;Kumar Y.;Tyagi K.D.;Kashyap A.

Performance Improvement of Double-Gate TFET Using Metal Strip Technique

Open Access
Article
Authors: Kumar S.;Nigam K.;Chaturvedi S.;Khan A.I.;Jain A.

Impact of gate overlap and underlap on analog/RF and linearity performance of dual-material gate-oxide-stack double-gate TFET

Open Access
Article

Negative Capacitance FET for Ultra Low Power Applications: A Review

Open Access
Conference Paper

Performance and Analysis of Stack Junctionless Tunnel Field Effect Transistor

Open Access
Article
Authors: Nigam K.;Kondekar P.;Chandan B.V.;Kumar S.;Tikkiwal V.A.;Dharmender ;Singh K.S.;Bhardwaj E.;Choubey S.;Chaturvedi S.