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Dr UDUTHA RAJENDER

vidwan id: 531011
Male

Professor, Electronics and Communication Engineering
Vageswari College of Engineering

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 18
Books 0
Proceedings 0

Publications

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Scopus

Citations 3
h-index 1

CrossRef

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Citations 6
h-index 1
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Professional Recognition

2020

Best Researcher Award

IJIEMR-ELSEVIER SSRN RESEARCH AWARDS -2020
2022

Best Thesis Award

Knowledge Research Academy
2018

ASSISTANT PROFESSOR

UGC NET

Community & Membership

2022

NAAC Criteria-2

Member

Indian Society for Technical Education (ISTE)

2024
Life Time

International Association of Engineers (IAENG)

2024
Life Time

Bio

I Studied B.Tech in Electronics and Communication Engineering from Jyothshmathi Institute of Technology & Science in 2009. i Studied M.Tech in VLSI Design from SRM University, Chennai in 2012. I Studied Ph.D in ECE from Sri satya Sai University of Technology and Medical Sciences in 2021. With the Research topic of Tunable Sub threshold Logic Design Through Adaptive feedback Equalization i Have a 4 years of research experience and more than 8 years of teaching experience. My research i

Personal Details

  • Male
  • Professor , Vageswari College of Engineering
  • Karimnagar, Telangana, India
PhD
Other Institute 2021
M.Tech
Other Institute 2012
B.Tech
Jyothishmathi Institute of Technology and Science 2009
Professor Aug 2021 – Present
Vageswari College of Engineering | Electronics and Communication Engineering
Assistant Professor Mar 2016 – May 2017
Vageswari College of Engineering
Assistant Professor Jul 2014 – Apr 2015
Trinity College of Engineering and Technology

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Organisations (28+)

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Co-Authors (2)

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Scholarly Work

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LOW-POWER, HIGH-SPEED VLSI SIGNAL PROCESSING FOR AI APPLICATIONS

Dr. Rajender Udutha
Engineering and Technology Patent No. : 10/2024 Filed : 02-02-2024
Published : 08-03-2024 Published

A CONNECTOR MODULE FOR A VLSI CIRCUIT WITH A BATTERY PACK

Centurion University of Technology and Management
Odisha
India
Engineering and Technology Application No. : 202141043814 A Filed : 17-09-2021
Published : 05-11-2021 Published

Scholarly Publications

GCS Publishers

Open Access
book
Authors: Dr. UDUTHA RAJENDER,Mr. sRIKANTH, Dr. ARUNKUMAR

Conventional Static Cmos Based Logic Circuits Design Through Adaptive Feedback Equalization

Open Access
article
Authors: Rajender Udutha1, Dr. A A Ansari2, Dr. S.Sreenath Kashyap3

Tunable Sub Threshold Logic Design Through Adaptive Feedback Equalization

Open Access
article
Authors: Rajender Udutha a, Dr. A A Ansari Dr. S.Sreenath Kashyapc
book
Authors: DR.UDUTHA RAJENDER

Tunable Subthreshold Logic Design Through Adaptive Feedback Equalization

Open Access
conference proceedings
Authors: RAJENDER UDUTHA,Dr. SrinathKashyap

DESIGNING A TUNABLE SUB THRESHOLD FLIP-FLOP THROUGH ADAPTIVE FEEDBACK EQUALIZATION

Open Access
conference proceedings
Authors: 1Rajender Udutha,2Dr.Srinath Kashyap

Delay Approximation Model for Prime Speed Interconnects in Current Mode

Open Access
article
Authors: Naraiah R, B.Balaji, Erigela Radhamma, Rajender Udutha

TUNABLE SUBTHRESHOLD LOGIC DESIGN THROUGH ADAPTIVE FEEDBACK EQUALIZATION

Open Access
article
Authors: 1UDUTHA RAJENDER, 2PADALA VANITHA