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Dr Pritesh Kumar Yadav

vidwan id: 507817
Male

Visiting Assistant Professor, Department of Electrical and Electronics engineering
Birla Institute of Technology and Science

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 9
Books 0
Proceedings 0

Publications

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Scopus

Citations 6
h-index 1

CrossRef

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Citations 15
h-index 2
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Bio

EEE

Personal Details

  • Male
  • Visiting Assistant Professor , Birla Institute of Technology and Science
  • Jai Jawahar Nagar Road, Arunodaya Nagar, Ambedkar Nagar, Sainikpuri, Secunderabad, Telangana, India
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Visiting Assistant Professor Feb 2024 – Present
Birla Institute of Technology and Science | Department of Electrical and Electronics engineering

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Co-Authors (3)

Manish

Prof Manish Goswami

Indian Institute of Information Technology, Allahabad

Prasanna Kumar

Dr Prasanna Kumar Mishra

Indian Institute of Information Technology, Allahabad

Sunanda

Dr Sunanda Ambulker

National Institute of Technology, Puducherry

Scholarly Work

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Scholarly Publications

A Differential LNA Architecture with Improved Figure of Merit Using 40 nm UMC CMOS Technology for mmWave Band Receiver Applications

Open Access
Article

A Double-Resistive Feedback Active Inductor based Receiver Frontend in 40 nm CMOS Process for 28-GHz Applications

Open Access
Conference Paper
Authors: Yadav P.K.;Misra P.K.

A 36.7 mW, 28 GHz receiver frontend using 40 nm RFCMOS technology with improved Figure of Merit

Open Access
Article

Tunable bandpass filter using double resistive feedback floating active inductor for 5 GHz wireless LAN Applications

Open Access
Article

A Proposed Technique to Improve the Performance of Receiver by Using Linear Gm-C Low-Pass Filter for mmwave Band Applications

Open Access
Article

Design of Transceiver at 865–867 MHz Band using UMC 180 nm CMOS Technology

Open Access
Conference Paper
Authors: Kumar J.S.;Kumari B.;Kumar P.;Verma A.;Yadav P.K.;Ambulker S.;Goswami M.;Misra P.K.

A 60 GHz, 50 mW, 3dB Noise Figure Receiver Frontend Using UMC 40 nm CMOS technology

Open Access
Conference Paper
Authors: Yadav P.K.;Kumar P.;Verma A.;Ambulker S.;Misra P.K.

Power Aware Study of 32-bit 5-stage Pipeline RISC CPU using 180nm CMOS Technology

Open Access
Conference Paper
Authors: Yadav P.K.;Misra P.K.