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Mr Swapnil Badar

vidwan id: 426810
Male

Assistant Professor, Electronics and Telecommunication Engineering
Shri Sant Gajanan Maharaj College of Engineering

Expertise

  • Computer Science Hardware and Architecture

Publications

Total Articles 5
Books 0
Proceedings 0

Publications

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Scopus

Citations 10
h-index 1

CrossRef

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Citations 1
h-index 1
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Professional Recognition

2023

Secured 1st Rank in AAWISHKAR-Project competition at District Level

SGBAU Amravati
2023

Elite Certificate with Silver Medal for NPTEL Certification Course on

NPTEL
2023

Summer Faculty Research Fellowship at IIT Delhi

IIT Delhi
2021

Best Paper award for the paper "Implementation of combinational logic for polar decoder"

ICORT-2021, ITR, DRDO, Chandipur
2020

Summer Faculty Research Fellowship at IIT Delhi

IIT Delh
2019

2nd rank for the project project “Design and Development of Analog Circuits using Unconventional CMOS Techniques for Biomedical Applications” at national level Cadence Design Contest Bangalore in Jan 2019.

Cadence, Bangalore
2024

Best Paper Award

ICCWC-2023 Springer Conference at NIT Jalandhar, Punjab

Community & Membership

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IEEE

2022
Graduate Student Member

IEEE

2021
Graduate Student Member

Bio

Analog and Digital VLSI

Personal Details

  • Male
  • Assistant Professor , Shri Sant Gajanan Maharaj College of Engineering
  • Department of Electronics and Telecommunication Engineering, SSGMCE, Shegaon
Ph.D. Pursuing
Other Institute 2024
Assistant Professor Jun 2015 – Present
Shri Sant Gajanan Maharaj College of Engineering | Electronics and Telecommunication Engineering

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Co-Authors (2)

KAMLESH

Dr KAMLESH KHANCHANDANI

Shri Sant Gajanan Maharaj College of Engineering

Pravin

Dr Pravin Wankhede

CSMSS Chh. Shahu College of Engineering

Scholarly Work

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Scholarly Publications

Efficient Implementation of Polar Decoder: Design and Performance Analysi

Open Access
book chapter
Authors: Swapnil P. Badar , Kamlesh Khanchandani

Fast Polar Decoder Implementation using Special Nodes

Open Access
Conference Paper
Authors: Swapnil P. Badar ., Kamlesh Khanchandani ., Pravin Wankhede .,

Successive Cancellation Polar Decoder Implementation using Processing Elements

Open Access
conference-paper
Authors:

Implementation of combinational logic for polar decoder

Open Access
Conference Paper

High speed FFT processor design using radix -<sup>4</sup> pipelined architecture

Open Access
Conference Paper