Ministry of Education
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Prof Shashidhara M

vidwan id: 370113
Male

Assistant Professor, Department of Electronics and Communication Engineering
PES UNIVERSITY, BANGLORE

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Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 22
Books 0
Proceedings 0

Publications

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Scopus

Citations 67
h-index 5

CrossRef

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Citations 50
h-index 5
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Professional Recognition

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Community & Membership

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Institute of Engineers India

2014
Regular

Bio

Spintronics, Magnetic memory design and modelling, nano-device modelling

Personal Details

  • Male
  • Assistant Professor , PES UNIVERSITY, BANGLORE
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Assistant Professor Mar 2023 – Present
PES UNIVERSITY, BANGLORE | Department of Electronics and Communication Engineering

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Scholarly Work

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Scholarly Publications

Comprehensive Investigation of Back Gate Biasing on Performance of Line TFETs

Open Access
Conference Paper
Year: 2023. Pages: 81-82 .
Authors: Panwar S.;Srivastava S.;Shashidhara M.;Dubey P.;Joshi D.;Acharya A.
DOI 10.23919/SNW57900.2023.10183969
2

Epitaxial Layer-Based Si/SiGe Hetero-Junction Line Tunnel FETs: A Physical Insight

Open Access
Book Chapter
Year: 2023. Pages: 165-186 .
Authors: Acharya A.;Panwar S.;Srivastava S.;Shashidhara M.
DOI 10.1002/9781394167647.ch8

Performance optimization of epitaxial-layer based Si/SiGe hetero-junction area scaled tunnel FET label-free biosensors considering steric hindrance

Open Access
Article
Year: 2023. Volume: 210 .
Authors: Panwar S.;Srivastava S.;M. S.;Joshi D.;Acharya A.
DOI 10.1016/j.sse.2023.108810
2 4

Understanding the Impact of Extension Region on Stacked Nanosheet FET: Analog Design Perspective

Open Access
Article
Year: 2023. Volume: 208 .
Authors: Srivastava S.;Shashidhara M.;Panwar S.;Yadav S.;Acharya A.
DOI 10.1016/j.sse.2023.108758
5 7

Spin-orbit torque magnetic tunnel junction based on 2-D materials: Impact of bias-layer on device performance

Open Access
Article
Year: 2023. Volume: 208 .
Authors: Shashidhara M.;Srivastava S.;Panwar S.;Acharya A.
DOI 10.1016/j.sse.2023.108757
1

Performance Investigation of Source/Drain Extension Region on Nanosheet FET: A Digital Design Perspective

Open Access
Conference Paper
Year: 2023. Pages: 79-80 .
Authors: Srivastava S.;Panwar S.;Shashidhara M.;Bagga N.;Joshi D.;Acharya A.
DOI 10.23919/SNW57900.2023.10183928
2 5

Comprehensive Investigation of Back Gate Biasing on Performance of Line TFETs

Open Access
conference-paper
Year: 2023. Pages: 81-82 .
Authors: Panwar, Sourabh;Srivastava, Shobhit;Shashidhara, M;Dubey, Prabhat;Joshi, Deepak;Acharya, Abhishek
2

Configurable 8T SRAM-based Computing In-Memory Architecture for Enabling Shift Operation and Multibit Dot-Product Engines

Open Access
Conference Paper
Year: 2023. Pages: 330-334 .
Authors: Yeswanth C.;Panwar S.;Srivastava S.;Joshi D.;Shashidhara M.;Acharya A.
DOI 10.1109/DevIC57758.2023.10134803