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Dr Ganesh Lakshman Kumar Moganti

vidwan id: 356057

Male

Associate Professor, School of Electronics Engineering
Vellore Institute of Technology (VIT-AP) University, Andhra Pradesh

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Expertise

Electrical and Electronic Engineering

Publications

Total Articles 25

Books 0

Proceedings 0

Publications

Scopus

Citations 47

h-index 4

CrossRef

Citations 10

h-index 2

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Professional Recognition

2022

International Distinguished Young Researcher Award 2021-22

International Institute of Organized Research (I2OR)

2022

Research Award for Publications

VIT-AP University

2022

Research Award for Patents

VIT-AP University

2021

BEST PAPER Awarded

11th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: T

2021

BEST PAPER Awarded

n 8th International Conference on Smart Computing and Communications (ICSCC2021)

2013

BEST PAPER Awarded

15th IEEE International Conference on Advanced Computing Technologies (ICACT-2013)

Community & Membership

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IEEE Membership

2023

IEEE Young Professionals

Bio

Highly committed Associate Professor with more than 11 years of B.Tech and M.Tech teaching experience at VIT-AP University(5+ years) and KIIT University(6 years). I have served in a key position, namely timetable coordinator, faculty coordinator of the photography club, course coordinator, lab-in charge, project guide for B.Tech and M.Tech students and student mentoring. I am currently pursuing my Ph.D. at IIT Hyderabad with a focus on the Fully Integrated Blink Restoration System for the Patien

Personal Details

Male
Associate Professor , Vellore Institute of Technology (VIT-AP) University, Andhra Pradesh
Chilakalapudi Road

Ph.D

Other Institute 2023

M.Tech

Other Institute 2012

B.Tech

Other Institute 2010

Associate Professor May 2018 – Present

Vellore Institute of Technology (VIT-AP) University, Andhra Pradesh | School of Electronics Engineering

Assistant Professor (Grade-I) Jun 2012 – Apr 2018

KIIT Deemed to be University, Bhubaneswar | School of Electronics Engineering

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Co-Authors (7)

Prof Ashudeb Dutta

Indian Institute of Technology Hyderabad

Dr Jitendra Kumar Das

Kalinga Institute of Industrial Technology, Bhubaneswar

Dr PURNA PRAKASH KASARANENI

N/A

Dr Y. V. Pavan Kumar

Vellore Institute of Technology (VIT-AP) University, Andhra Pradesh

Dr Sameeulla Khan Md

Vellore Institute of Technology (VIT-AP) University, Andhra Pradesh

Prof Sushanta Kumar Mandal

Adamas University

Dr Siva Rama Krishna Vanjari

Indian Institute of Technology Hyderabad

Scholarly Work

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A 1.4 DB NF DUAL CURRENT REUSE BASED LOW NOISE AMPLIFIER (LNA) DESIGN

VIT-AP University

Engineering and Technology Application No. : 202141057911 Filed : 13-12-2021

Published : 24-12-2021 Published

A Hybrid Charge Balancing Technique with Adaptive ETI Impedance Variations for Facial Paralysis Patients

VIT-AP University

Engineering and Technology Application No. : 202141038641 Filed : 26-08-2021

Published : 10-09-2021 Published

An Implantable Bipolar Active Charge Balancing Circuit with Six Adjustment Current levels for Facial Paralysis Patients

VIT-AP University

Engineering and Technology Application No. : 202141030639 Filed : 08-07-2021

Published : 23-07-2021 Published

Scholarly Publications

Low Power Emg Front-End for Face Paralysis

Conference Paper

Authors:

DOI

10.1109/ICAECC.2018.8479503

High resolution reconfigurable bio-potential processor for portable biomedical application

Conference Paper

Year: 2017. Pages: 517-521 .

Authors: Senapati B.;Kumar M.G.L.;Ray K.B.

2

Low power, low area, analog blink restoration system with auto sleep mode for unilateral facial paralysis patients

Conference Paper

Year: 2017. Volume: 2018-January , Pages: 1-4 .

Authors: Kumar M.G.L.;Sairam R.S.;Kumar G.D.V.S.;Vanjari S.R.K.

DOI

10.1109/BIOCAS.2017.8325064

2

1

Fully integrated sub-threshold body biased low noise portable ECG frontend

Conference Paper

Authors:

Design of current reuse based Differential Merged LNA-Mixer (DMLNAM) and two-stage Dual Band LNA with two gain modes in 65nm technology

Conference Paper

Year: 2016. Volume: 2016-April , Pages: 98-103 .

Authors: Ganesh Lakshmana Kumar M.;Regulagadda S.S.;Das J.K.;Dutta A.

DOI

10.1109/PrimeAsia.2015.7450478

3

6

Design of a high speed and low area latch-based comparator in 90-nm CMOS technology having low offset voltage

Conference Paper

Year: 2016. Pages: 628-631 .

Authors:

DOI

10.1109/ICESA.2015.7503425

A novel design of a high speed hysteresis-based comparator in 90-nm CMOS technology

Conference Paper

Year: 2016. Pages: 388-391 .

Authors:

13

Comparison of serial data-input CRC and parallel data-input CRC design for CRC-8 ATM HEC employing MLFSR

Conference Paper

Authors:

2

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