Ministry of Education
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Dr Sudhanya P

vidwan id: 315350
Female

Assistant Professor,

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Expertise

  • Communication

Publications

Total Articles 7
Books 0
Proceedings 0

Publications

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Scopus

Citations 15
h-index 2

CrossRef

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Citations 10
h-index 1
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Professional Recognition

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Community & Membership

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The Institution of Engineers (India)

2023
Associate Member

Bio

VLSI Design

Personal Details

  • Female
  • Assistant Professor
  • 5/479, Saraswathi Street, Madipakkam
PhD
Other Institute 2022
Assistant Professor Aug 2022 – Present
Unknown Organization

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Organisation (0)

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Co-Authors (2)

S P

Dr S P Joy Vasantha Rani

Anna University

Muthu

Dr Muthu Krishnammal

Vellore Institute of Technology (VIT-AP) University, Andhra Pradesh

Scholarly Work

Performance Enhancement in FPGA Architecture by Efficient Design of Logic Blocks

Funding Agency: Department of Science and Technology, Govt. of India

Principal Investigator

2,064,480

2018 - 2021

Completed
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Scholarly Publications

Approximate Multipliers Design Using Approximate Adders for Image Processing Applications

Open Access
Article
Year: 2022. Volume: 31 , Issue: 15 .
Authors: Joy Vasantha Rani S.P.;Lourdu Jennifer J.R.;Sudhanya P.
DOI 10.1142/S0218126622502565
1 1

Wire-Length and Run-Time Optimization in FPGA Placement Using Hybrid Iterative Algorithms

Open Access
Article
Year: 2021. Volume: 30 , Issue: 5 .
Authors: Sudhanya P.;Rani S.P.J.V.
DOI 10.1142/S021812662150081X
1 3

Adaptive Particle Swarm Optimization Based Wire-length Minimization for Placement in FPGA

Open Access
Conference Paper
Year: 2020. Pages: 793-801 .
Authors: Sudhanya P.;Joy Vasantha Rani S.P.
DOI 10.1007/978-3-030-41862-5_79
1 2

Fast and Memory Compact Routing Algorithm for FPGA

Open Access
Conference Paper
Year: 2019.
Authors: Sudhanya P.;Rani S.P.J.V.;Ali S.D.
DOI 10.1109/ICESIP46348.2019.8938275
1 1

Design of Logic Blocks for Efficient Architecture of FPGA

Open Access
Conference Paper
Year: 2019.
Authors: Sudhanya P.;Rani S.P.J.V.;Lavanya M.C.
DOI 10.1109/ICESIP46348.2019.8938291
1 2

Design of silicon Physical Unclonable Function for authentication of a multicore device

Open Access
Article
Year: 2016. Volume: 7 , Issue: 3 , Pages: 933-941 .
Authors: Sudhanya P.;Muthu Krishnammal P.

Study of different silicon Physical Unclonable Functions

Open Access
Conference Paper
Year: 2016. Pages: 81-85 .
Authors: P. Muthu Krishnammal .,
DOI 10.1109/WiSPNET.2016.7566095
5 6