Ministry of Education
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Dr Radhika P

vidwan id: 306977
Female

Assistant Professor, Department of Electronics and Communication Engineering - KTR
S R M Institute of Science & Technology, Chennai

Orchid Icon 0000-0001-7479-2301 Google Scholar Icon 55608882000 Researcher Icon AAE-7824-2021 Google Scholar Icon I1hkviYAAAAJ

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 28
Books 0
Proceedings 0

Publications

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Scopus

Citations 158
h-index 4

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Citations 0
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Bio

VLSI,Signal Processing

Personal Details

  • Female
  • Assistant Professor , S R M Institute of Science & Technology, Chennai
  • Department of Electronics and Communication Engineering, SRM Institute of Science and Technology
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Assistant Professor Jun 2004 – Present
S R M Institute of Science & Technology, Chennai | Department of Electronics and Communication Engineering - KTR

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Scholarly Work

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Scholarly Publications

Towards accurate diagnosis: exploring knowledge distillation and self-attention in multimodal medical image fusion

Open Access
Article
Year: 2024.
Authors: Radhika P ., Sofia Bobby J ., Sheeja V. Francis ., Femina M. A .,
DOI 10.1080/0952813X.2024.2396131

Design of a high-speed MCML D-Latch at 0.6 V in 45 nm CMOS technology

Open Access
Article
Year: 2024. Volume: 15 , Issue: 2 , Pages: 1052-1060 .
Authors: Sivasakthi Madheswaran ., Radhika Panneerselvam .,
DOI 10.11591/ijpeds.v15.i2.pp1052-1060

Hybrid machine learning-based breast cancer segmentation framework using ultrasound images with optimal weighted features

Open Access
Article
Year: 2024. Volume: 42 , Issue: 4 .
Authors: Sudharsana Vijayan ., Radhika Panneerselvam ., Thundi Valappil Roshini .,
DOI 10.1002/cbf.4054

Sentiment Classification of Product Reviews using Machine Learning

Open Access
Conference Paper
Year: 2024.
Authors: Vedullapalli Adarsh ., Vaibhav Mohla ., Ragven Kumar Mahto ., Radhika P .,
DOI 10.1109/RAEEUCCI61380.2024.10547858

Design and analysis of 7-stage MOS current mode logic power gated MOSFETs in current starved voltage-controlled oscillator for the phase locked loop application

Open Access
Article
Year: 2024. Volume: 14 , Issue: 2 , Pages: 1398-1405 .
Authors: Sivasakthi Madheswaran ., Radhika Panneerselvam .,
DOI 10.11591/ijece.v14i2.pp1398-1405
1

A high-speed MCML charge pump design at 10 GHz frequency in 45 nm CMOS technology for PLL application

Open Access
Article
Analog Integrated Circuits and Signal Processing. Year: 2024. Volume: 118 , Issue: 1 , Pages: 49-66 .
Authors: M. Sivasakthi ., P. Radhika .,
DOI 10.1007/s10470-023-02225-0

Design and analysis of PVT tolerant hybrid current starved ring VCO with bulk driven keeper technique at 45 nm CMOS technology for the PLL application

Open Access
Article
AEU - International Journal of Electronics and Communications. Year: 2024. Volume: 173 .
Authors: M. Sivasakthi ., P. Radhika .,
DOI 10.1016/j.aeue.2023.154987
6

Performance Comparison of MCML, PFSCL, and Dynamic CML Gates with Parametric Analysis in 45 nm CMOS Technology

Open Access
Conference Paper
Year: 2023. Volume: 977 , Pages: 451-463 .
Authors: Sivasakthi M.;Radhika P.
DOI 10.1007/978-981-19-7753-4_35
3