Ministry of Education
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Dr Ajay Kumar Dadoria

vidwan id: 300255
Male

Assistant Professor, Department of Electronics and Communication Engineering
Amity University, Gwalior

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Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 24
Books 0
Proceedings 0

Publications

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Scopus

Citations 127
h-index 6

CrossRef

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Citations 99
h-index 5
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Bio

Low Power VLSI Design

Personal Details

  • Male
  • Assistant Professor , Amity University, Gwalior
  • Department of Electronics and Communication Engineering,Amity University,Gwalior
Ph.D
Other Institute 2018
Assistant Professor Feb 2018 – Present
Amity University, Gwalior | Department of Electronics and Communication Engineering

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Scholarly Work

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Scholarly Publications

Design of Low-Power Dynamic Type Latch Comparator Using 18 nm FinFET Technology for SAR ADC

Open Access
Conference Paper
Year: 2021. Pages: 603-609 .
Authors: Hemalatha B.;Dadoria A.K.
DOI 10.1007/978-981-33-4684-0_61
1 1

Design and Analysis of CNTFET based VLSI Interconnects by Using PVT Variation

Open Access
other
Year: 2021.
Authors:

Comparative temporal metabolomics studies to investigate interspecies variation in three Ocimum species

Open Access
Article
Scientific Reports. Year: 2020. Volume: 10 , Issue: 1 .
Authors: Shubhra Rastogi ., Saumya Shah ., Ritesh Kumar ., Ajay Kumar ., Ajit Kumar Shasany .,
DOI 10.1038/s41598-020-61957-5
28 16

Techniques for sigma delta ADC design using CMOS technology for CODEC

Open Access
Article
Year: 2019. Volume: 8 , Issue: 9 Special Issue 2 , Pages: 9-13 .
Authors: Hemalatha B.;Dadoria A.K.;Srivastava H.
DOI 10.35940/ijitee.I1003.0789S219

Design and Analysis of Low-Power Adiabatic Logic Circuits by Using CNTFET Technology

Open Access
Article
Year: 2019. Volume: 38 , Issue: 9 , Pages: 4338-4356 .
Authors: Dadoria A.K.;Khare K.
DOI 10.1007/s00034-019-01059-4
4 12

A novel adiabatic technique for energy efficient logic circuits design

Open Access
Conference Paper
Year: 2018. Pages: 449-455 .
Authors: Chugh C.;Kaur P.;Gupta T.K.;Dadoria A.K.
DOI 10.1109/ICICS.2018.00097
1 2

Integrating flipped drain and power gating techniques for efficient FinFET logic circuits

Open Access
Article
Year: 2018. Volume: 31 , Issue: 5 .
Authors: Dadoria A.K.;Khare K.;Gupta T.K.;Panwar U.
DOI 10.1002/jnm.2344
1 4

Low power high speed 1-bit full adder circuit design in DSM technology

Open Access
Conference Paper
Year: 2018. Volume: 2018-January , Pages: 1-6 .
Authors: Ashish Yadav ., Bhawna P. Shrivastava ., Ajay Kumar Dadoria .,
DOI 10.1109/ICOMICON.2017.8279098
1 1