Ministry of Education
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Mr Vijay Sai Radhakrishnan

vidwan id: 293686
Male

Assistant Professor, Department of Information and Communication Technology
Shanmugha Arts, Science, Technology & Reserch Academy (SASTRA), Thanjavur

Orchid Icon 0000-0002-2549-5092 Google Scholar Icon 54783724300 Google Scholar Icon RlTAoG0AAAAJ

Expertise

  • Computer Science Information Systems

Publications

Total Articles 16
Books 0
Proceedings 0

Publications

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Scopus

Citations 38
h-index 3

CrossRef

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Citations 14
h-index 2
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Bio

VLSI

Personal Details

  • Male
  • Assistant Professor , Shanmugha Arts, Science, Technology & Reserch Academy (SASTRA), Thanjavur
  • SASTRA Deemed University, Tirumalaisamudram
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Assistant Professor Dec 2006 – Present
Shanmugha Arts, Science, Technology & Reserch Academy (SASTRA), Thanjavur | Department of Information and Communication Technology

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Co-Authors (3)

Lavanya

Dr Lavanya M

Shanmugha Arts, Science, Technology & Reserch Academy (SASTRA), Thanjavur

Saravanan

Dr Saravanan S

Shanmugha Arts, Science, Technology & Reserch Academy (SASTRA), Thanjavur

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Dr Vaithiyanadhan V

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Scholarly Work

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Scholarly Publications

Improving security against cache memory attacks for dual field multiplier design based on elliptic curve cryptography

Open Access
Article
Journal of Ambient Intelligence and Humanized Computing. Year: 2021.
Authors: Vijay Sai R.;Upadhyay H.N.
DOI 10.1007/s12652-020-02830-1

Undeviating Adaptive Sheltered Cryptography (UASC) method based low power and high secure cache memory design

Open Access
Article
Microprocessors and Microsystems. Year: 2019. Volume: 71 .
Authors: Sai R.V.;Upadhyay H.N.;Prabhu M.;Saravanan S.
DOI 10.1016/j.micpro.2019.102876
2 2

Memristor based data retention flip-flop

Open Access
Article
Year: 2017. Volume: 17 , Issue: 1 , Pages: 73-83 .
Authors: Sai R.V.;Saravanan S.
DOI 10.17654/EC017010073

Improving the reliability of cache memories using identical tag bits

Open Access
Article
Indian Journal of Science and Technology. Year: 2016. Volume: 9 , Issue: 29 .
Authors: Manju Bharathi S.;Vijay Sai R.;Saravanan S.
DOI 10.17485/ijst/2016/v9i29/90864
2

Cell stability and power reduction using dynamic isolated read static random access memory

Open Access
Article
Indian Journal of Science and Technology. Year: 2016. Volume: 9 , Issue: 29 .
Authors: Vandhana M.;Vijay Sai R.;Saravanan S.
DOI 10.17485/ijst/2016/v9i29/90875
1 2

An encryption algorithm functioning on ASCII values and random number generation

Open Access
Article
Indian Journal of Science and Technology. Year: 2015. Volume: 8 , Issue: 35 .
Authors: Lavanya M.;Vijay Sai R.;Festina A.;Eshwari J.;Manopriya T.;Vaithiyanathan V.
DOI 10.17485/ijst/2015/v8i35/86673
2 3

Implementation of a novel data scrambling based security measure in memories for VLSI circuits

Open Access
Article
Indian Journal of Science and Technology. Year: 2015. Volume: 8 , Issue: 35 .
Authors: Vijay Sai R.;Saravanan S.;Anandkumar V.
DOI 10.17485/ijst/2015/v8i35/IPL1024
3