Ministry of Education
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Mr Nirmalraj T

vidwan id: 293456
Male

Associate Professor, Department of Electronics and Communication Engineering
Shanmugha Arts, Science, Technology & Reserch Academy (SASTRA), Thanjavur

Orchid Icon 0000-0001-5293-4452 Google Scholar Icon 57189307344 Google Scholar Icon rQQ3L8MAAAAJ

Expertise

  • Electrical and Electronic Engineering

Publications

Total Articles 10
Books 0
Proceedings 0

Publications

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Scopus

Citations 12
h-index 2

CrossRef

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Citations 8
h-index 2
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Bio

VLSI DESIGN-VLSI Design of Low Power And High-Speed Arithmetic Circuit With Built-In Memory System

Personal Details

  • Male
  • Associate Professor , Shanmugha Arts, Science, Technology & Reserch Academy (SASTRA), Thanjavur
  • SASTRA Deemed University, Tirumalaisamudram
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Associate Professor Jul 2008 – Present
Shanmugha Arts, Science, Technology & Reserch Academy (SASTRA), Thanjavur | Department of Electronics and Communication Engineering

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Co-Authors (4)

V

Dr V Elamaran

Shanmugha Arts, Science, Technology & Reserch Academy (SASTRA), Thanjavur

Radhakrishnan

Dr Radhakrishnan S

Shanmugha Arts, Science, Technology & Reserch Academy (SASTRA), Thanjavur

Jayalalitha

Prof Jayalalitha Subbaiah

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Rajendran

Mr Rajendran V G

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Scholarly Work

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Scholarly Publications

Automatic diagnosis of single fault in interconnect testing of sram-based FPGA

Open Access
Article
Year: 2021. Volume: 15 , Issue: 5 , Pages: 362-371 .
Authors: Nirmalraj T.;Radhakrishnan S.;Pandiyan S.K.
DOI 10.1049/cdt2.12028

Development of single channel eeg acquisition system for bci applications

Open Access
Article
Year: 2021. Volume: 14 , Issue: 9 , Pages: 4705-4709 .
Authors: Rajendran V.G.;Jayalalitha S.;Adalarasu K.;Nirmalraj T.
DOI 10.52711/0974-360X.2021.00818
1 1

An efficient design for area-efficient truncated adaptive booth multiplier for signal processing applications

Open Access
Article
Journal of Circuits, Systems and Computers. Year: 2021. Volume: 30 , Issue: 3 .
Authors: Radhakrishnan S.;Karn R.K.;Nirmalraj T.
DOI 10.1142/S0218126621500377
1 1

Design of Low Power and High Speed MAC based FIR Filter using Hybrid Adder and Modified Booth Multiplier

Open Access
Conference Paper
Year: 2020.
Authors: Radhakrishnan S.;Karn R.K.;Meerasha M.A.;Nirmalraj T.
DOI 10.1109/ICEE50728.2020.9776857

An enhanced Gate Diffusion Input technique for low power applications

Open Access
Article
Microelectronics Journal. Year: 2019. Volume: 93 .
Authors: Radhakrishnan S.;Nirmalraj T.;karn R.k.
DOI 10.1016/j.mejo.2019.104621
2 2

Fault Tolerant Carry Save Adders - A NMR Configuration Approach

Open Access
Conference Paper
Year: 2018. Pages: 210-215 .
Authors: Radhakrishnan S.;Nirmalraj T.;Ashwin S.;Elamaran V.;Karn R.K.
DOI 10.1109/ICCPCCT.2018.8574227
2 3

Design of low power, high speed PLL frequency synthesizer using dynamic CMOS VLSI technology

Open Access
Conference Paper
Year: 2018. Pages: 1074-1076 .
Authors: Nirmalraj T.;Radhakrishnan S.;Karn R.K.;Pandiyan S.K.
DOI 10.1109/ICPCSI.2017.8391875
2

Low latency power aware selfchecking based CSA for sequential multiplier

Open Access
Conference Paper
Year: 2018. Pages: 1056-1059 .
Authors: Radhakrishnan S.;Nirmalraj T.;Karn R.K.;Pandiyan S.K.
DOI 10.1109/ICPCSI.2017.8391872
2 2